mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-11-22 04:56:15 +00:00
1c61a8f958
Hardware -------- RockChip RK3588 ARM64 (8 cores) 4/8/16/32GB LPDDR4X RAM 2500 Base-T RGB LED eMMC Connector SPI-NOR 16MB Micro-SD Slot 2x USB 2.0 Port 2x USB 3.0 Port Headphone Jack M.2 E-Key M.2 M-Key USB PD 5/9/12/15/20V Power Install -------- Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/16149 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
74 lines
1.9 KiB
Diff
74 lines
1.9 KiB
Diff
From 199cbd5f195adbc0e70ad218cdba82f45750f11b Mon Sep 17 00:00:00 2001
|
|
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
|
Date: Mon, 18 Sep 2023 16:14:50 +0200
|
|
Subject: [PATCH] arm64: dts: rockchip: add PCIe for M.2 M-key to rock-5b
|
|
|
|
The Radxa Rock 5B has PCIe 3x4 routed to its M.2 M-key connector
|
|
on the board's back.
|
|
|
|
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
|
Link: https://lore.kernel.org/r/20230918141451.131247-3-sebastian.reichel@collabora.com
|
|
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
|
---
|
|
.../boot/dts/rockchip/rk3588-rock-5b.dts | 35 +++++++++++++++++++
|
|
1 file changed, 35 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
|
|
@@ -52,6 +52,19 @@
|
|
vin-supply = <&vcc_3v3_s3>;
|
|
};
|
|
|
|
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
|
|
+ compatible = "regulator-fixed";
|
|
+ enable-active-high;
|
|
+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pcie3_vcc3v3_en>;
|
|
+ regulator-name = "vcc3v3_pcie30";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ startup-delay-us = <5000>;
|
|
+ vin-supply = <&vcc5v0_sys>;
|
|
+ };
|
|
+
|
|
vcc5v0_host: vcc5v0-host-regulator {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "vcc5v0_host";
|
|
@@ -224,6 +237,18 @@
|
|
status = "okay";
|
|
};
|
|
|
|
+&pcie30phy {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pcie3x4 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pcie3_rst>;
|
|
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
|
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
&pinctrl {
|
|
hym8563 {
|
|
hym8563_int: hym8563-int {
|
|
@@ -243,6 +268,16 @@
|
|
};
|
|
};
|
|
|
|
+ pcie3 {
|
|
+ pcie3_rst: pcie3-rst {
|
|
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ pcie3_vcc3v3_en: pcie3-vcc3v3-en {
|
|
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
usb {
|
|
vcc5v0_host_en: vcc5v0-host-en {
|
|
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|