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6a0a6c45ed
Backport upstreamed dts updates for rk3588. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/16149 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
141 lines
3.7 KiB
Diff
141 lines
3.7 KiB
Diff
From 667885a6865832eb0678c7e02e47a3392f177ecb Mon Sep 17 00:00:00 2001
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From: Alexey Charkov <alchark@gmail.com>
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Date: Mon, 17 Jun 2024 22:28:57 +0400
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Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588j
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RK3588j is the 'industrial' variant of RK3588, and it uses a different
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set of OPPs both in terms of allowed frequencies and in terms of
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applicable voltages at each frequency setpoint.
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Add the OPPs that apply to RK3588j (and apparently RK3588m too) to
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enable dynamic CPU frequency scaling.
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OPP values are derived from Rockchip downstream sources [1] by taking
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only those OPPs which have the highest frequency for a given voltage
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level and dropping the rest (if they are included, the kernel complains
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at boot time about them being inefficient)
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[1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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Signed-off-by: Alexey Charkov <alchark@gmail.com>
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Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-7-c1f5f3267f1e@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 108 ++++++++++++++++++++++
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1 file changed, 108 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
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@@ -5,3 +5,111 @@
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*/
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#include "rk3588-extra.dtsi"
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+
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+/ {
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+ cluster0_opp_table: opp-table-cluster0 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-1416000000 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <750000 750000 950000>;
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+ clock-latency-ns = <40000>;
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+ opp-suspend;
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+ };
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+ opp-1608000000 {
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+ opp-hz = /bits/ 64 <1608000000>;
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+ opp-microvolt = <887500 887500 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1704000000 {
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+ opp-hz = /bits/ 64 <1704000000>;
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+ opp-microvolt = <937500 937500 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ };
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+
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+ cluster1_opp_table: opp-table-cluster1 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-1416000000 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <750000 750000 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1608000000 {
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+ opp-hz = /bits/ 64 <1608000000>;
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+ opp-microvolt = <787500 787500 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1800000000 {
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+ opp-hz = /bits/ 64 <1800000000>;
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+ opp-microvolt = <875000 875000 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-2016000000 {
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+ opp-hz = /bits/ 64 <2016000000>;
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+ opp-microvolt = <950000 950000 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ };
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+
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+ cluster2_opp_table: opp-table-cluster2 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-1416000000 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <750000 750000 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1608000000 {
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+ opp-hz = /bits/ 64 <1608000000>;
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+ opp-microvolt = <787500 787500 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1800000000 {
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+ opp-hz = /bits/ 64 <1800000000>;
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+ opp-microvolt = <875000 875000 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-2016000000 {
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+ opp-hz = /bits/ 64 <2016000000>;
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+ opp-microvolt = <950000 950000 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ };
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+};
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+
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+&cpu_b0 {
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+ operating-points-v2 = <&cluster1_opp_table>;
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+};
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+
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+&cpu_b1 {
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+ operating-points-v2 = <&cluster1_opp_table>;
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+};
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+
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+&cpu_b2 {
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+ operating-points-v2 = <&cluster2_opp_table>;
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+};
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+
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+&cpu_b3 {
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+ operating-points-v2 = <&cluster2_opp_table>;
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+};
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+
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+&cpu_l0 {
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+ operating-points-v2 = <&cluster0_opp_table>;
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+};
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+
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+&cpu_l1 {
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+ operating-points-v2 = <&cluster0_opp_table>;
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+};
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+
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+&cpu_l2 {
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+ operating-points-v2 = <&cluster0_opp_table>;
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+};
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+
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+&cpu_l3 {
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+ operating-points-v2 = <&cluster0_opp_table>;
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+};
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