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6a0a6c45ed
Backport upstreamed dts updates for rk3588. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/16149 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
206 lines
5.8 KiB
Diff
206 lines
5.8 KiB
Diff
From 276856db91b46eaa7a4c19226c096a9dc899a3e9 Mon Sep 17 00:00:00 2001
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From: Alexey Charkov <alchark@gmail.com>
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Date: Mon, 17 Jun 2024 22:28:56 +0400
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Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588
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By default the CPUs on RK3588 start up in a conservative performance
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mode. Add frequency and voltage mappings to the device tree to enable
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dynamic scaling via cpufreq.
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OPP values are adapted from Radxa's downstream kernel for Rock 5B [1],
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stripping them down to the minimum frequency and voltage combinations
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as expected by the generic upstream cpufreq-dt driver, and also dropping
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those OPPs that don't differ in voltage but only in frequency (keeping
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the top frequency OPP in each case).
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Note that this patch ignores voltage scaling for the CPU memory
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interface which the downstream kernel does through a custom cpufreq
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driver, and which is why the downstream version has two sets of voltage
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values for each OPP (the second one being meant for the memory
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interface supply regulator). This is done instead via regulator
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coupling between CPU and memory interface supplies on affected boards.
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This has been tested on Rock 5B with u-boot 2023.11 compiled from
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Collabora's integration tree [2] with binary bl31 and appears to be
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stable both under active cooling and passive cooling (with throttling)
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[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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[2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot
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Signed-off-by: Alexey Charkov <alchark@gmail.com>
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Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-6-c1f5f3267f1e@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 149 +++++++++++++++++++
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arch/arm64/boot/dts/rockchip/rk3588.dtsi | 1 +
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 +
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3 files changed, 151 insertions(+)
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
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@@ -0,0 +1,149 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+
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+/ {
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+ cluster0_opp_table: opp-table-cluster0 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <675000 675000 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <712500 712500 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1416000000 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <762500 762500 950000>;
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+ clock-latency-ns = <40000>;
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+ opp-suspend;
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+ };
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+ opp-1608000000 {
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+ opp-hz = /bits/ 64 <1608000000>;
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+ opp-microvolt = <850000 850000 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1800000000 {
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+ opp-hz = /bits/ 64 <1800000000>;
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+ opp-microvolt = <950000 950000 950000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ };
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+
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+ cluster1_opp_table: opp-table-cluster1 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <675000 675000 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1416000000 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <725000 725000 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1608000000 {
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+ opp-hz = /bits/ 64 <1608000000>;
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+ opp-microvolt = <762500 762500 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1800000000 {
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+ opp-hz = /bits/ 64 <1800000000>;
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+ opp-microvolt = <850000 850000 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-2016000000 {
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+ opp-hz = /bits/ 64 <2016000000>;
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+ opp-microvolt = <925000 925000 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-2208000000 {
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+ opp-hz = /bits/ 64 <2208000000>;
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+ opp-microvolt = <987500 987500 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-2400000000 {
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+ opp-hz = /bits/ 64 <2400000000>;
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+ opp-microvolt = <1000000 1000000 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ };
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+
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+ cluster2_opp_table: opp-table-cluster2 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <675000 675000 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1416000000 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <725000 725000 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1608000000 {
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+ opp-hz = /bits/ 64 <1608000000>;
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+ opp-microvolt = <762500 762500 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-1800000000 {
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+ opp-hz = /bits/ 64 <1800000000>;
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+ opp-microvolt = <850000 850000 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-2016000000 {
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+ opp-hz = /bits/ 64 <2016000000>;
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+ opp-microvolt = <925000 925000 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-2208000000 {
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+ opp-hz = /bits/ 64 <2208000000>;
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+ opp-microvolt = <987500 987500 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp-2400000000 {
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+ opp-hz = /bits/ 64 <2400000000>;
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+ opp-microvolt = <1000000 1000000 1000000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ };
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+};
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+
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+&cpu_b0 {
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+ operating-points-v2 = <&cluster1_opp_table>;
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+};
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+
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+&cpu_b1 {
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+ operating-points-v2 = <&cluster1_opp_table>;
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+};
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+
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+&cpu_b2 {
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+ operating-points-v2 = <&cluster2_opp_table>;
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+};
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+
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+&cpu_b3 {
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+ operating-points-v2 = <&cluster2_opp_table>;
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+};
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+
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+&cpu_l0 {
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+ operating-points-v2 = <&cluster0_opp_table>;
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+};
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+
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+&cpu_l1 {
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+ operating-points-v2 = <&cluster0_opp_table>;
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+};
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+
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+&cpu_l2 {
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+ operating-points-v2 = <&cluster0_opp_table>;
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+};
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+
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+&cpu_l3 {
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+ operating-points-v2 = <&cluster0_opp_table>;
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+};
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--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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@@ -5,3 +5,4 @@
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*/
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#include "rk3588-extra.dtsi"
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+#include "rk3588-opp.dtsi"
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -5,3 +5,4 @@
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*/
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#include "rk3588-base.dtsi"
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+#include "rk3588-opp.dtsi"
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