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6a0a6c45ed
Backport upstreamed dts updates for rk3588. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/16149 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
121 lines
3.0 KiB
Diff
121 lines
3.0 KiB
Diff
From d895dbef3f3a31ab50491bb48552e798cf555987 Mon Sep 17 00:00:00 2001
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From: Andy Yan <andy.yan@rock-chips.com>
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Date: Mon, 11 Dec 2023 20:00:04 +0800
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Subject: [PATCH] arm64: dts: rockchip: Add vop on rk3588
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Add vop dt node for rk3588.
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Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
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Link: https://lore.kernel.org/r/20231211120004.1785616-1-andyshrk@163.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 83 +++++++++++++++++++++++
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1 file changed, 83 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -394,6 +394,11 @@
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#clock-cells = <0>;
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};
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+ display_subsystem: display-subsystem {
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+ compatible = "rockchip,display-subsystem";
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+ ports = <&vop_out>;
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+ };
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+
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
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@@ -506,6 +511,16 @@
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reg = <0x0 0xfd58c000 0x0 0x1000>;
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};
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+ vop_grf: syscon@fd5a4000 {
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+ compatible = "rockchip,rk3588-vop-grf", "syscon";
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+ reg = <0x0 0xfd5a4000 0x0 0x2000>;
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+ };
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+
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+ vo1_grf: syscon@fd5a8000 {
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+ compatible = "rockchip,rk3588-vo-grf", "syscon";
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+ reg = <0x0 0xfd5a8000 0x0 0x100>;
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+ };
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+
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php_grf: syscon@fd5b0000 {
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compatible = "rockchip,rk3588-php-grf", "syscon";
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reg = <0x0 0xfd5b0000 0x0 0x1000>;
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@@ -625,6 +640,74 @@
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status = "disabled";
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};
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+ vop: vop@fdd90000 {
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+ compatible = "rockchip,rk3588-vop";
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+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
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+ reg-names = "vop", "gamma-lut";
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+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_VOP>,
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+ <&cru HCLK_VOP>,
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+ <&cru DCLK_VOP0>,
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+ <&cru DCLK_VOP1>,
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+ <&cru DCLK_VOP2>,
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+ <&cru DCLK_VOP3>,
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+ <&cru PCLK_VOP_ROOT>;
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+ clock-names = "aclk",
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+ "hclk",
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+ "dclk_vp0",
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+ "dclk_vp1",
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+ "dclk_vp2",
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+ "dclk_vp3",
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+ "pclk_vop";
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+ iommus = <&vop_mmu>;
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+ power-domains = <&power RK3588_PD_VOP>;
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+ rockchip,grf = <&sys_grf>;
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+ rockchip,vop-grf = <&vop_grf>;
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+ rockchip,vo1-grf = <&vo1_grf>;
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+ rockchip,pmu = <&pmu>;
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+ status = "disabled";
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+
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+ vop_out: ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ vp0: port@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+ };
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+
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+ vp1: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+ };
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+
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+ vp2: port@2 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <2>;
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+ };
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+
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+ vp3: port@3 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <3>;
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+ };
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+ };
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+ };
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+
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+ vop_mmu: iommu@fdd97e00 {
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+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
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+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
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+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
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+ clock-names = "aclk", "iface";
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+ #iommu-cells = <0>;
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+ power-domains = <&power RK3588_PD_VOP>;
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+ status = "disabled";
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+ };
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+
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uart0: serial@fd890000 {
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compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
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reg = <0x0 0xfd890000 0x0 0x100>;
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