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7108f5bd9f
Backport upstreamed clk/mfd/phy/usb updates for rk3588. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/16149 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
107 lines
4.3 KiB
Diff
107 lines
4.3 KiB
Diff
From a1fe1eca0d8be69ccc1f3d615e5a529df1c82e66 Mon Sep 17 00:00:00 2001
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From: Niklas Cassel <cassel@kernel.org>
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Date: Fri, 12 Apr 2024 14:58:16 +0200
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Subject: [PATCH] phy: rockchip-snps-pcie3: add support for
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rockchip,rx-common-refclk-mode
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>From the RK3588 Technical Reference Manual, Part1,
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section 6.19 PCIe3PHY_GRF Register Description:
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"rxX_cmn_refclk_mode"
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RX common reference clock mode for lane X. This mode should be enabled
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only when the far-end and near-end devices are running with a common
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reference clock.
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The hardware reset value for this field is 0x1 (enabled).
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Note that this register field is only available on RK3588, not on RK3568.
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The link training either fails or is highly unstable (link state will jump
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continuously between L0 and recovery) when this mode is enabled while
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using an endpoint running in Separate Reference Clock with No SSC (SRNS)
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mode or Separate Reference Clock with SSC (SRIS) mode.
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(Which is usually the case when using a real SoC as endpoint, e.g. the
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RK3588 PCIe controller can run in both Root Complex and Endpoint mode.)
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Add support for the device tree property rockchip,rx-common-refclk-mode,
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such that the PCIe PHY can be used in configurations where the Root
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Complex and Endpoint are not using a common reference clock.
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Signed-off-by: Niklas Cassel <cassel@kernel.org>
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Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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.../phy/rockchip/phy-rockchip-snps-pcie3.c | 37 +++++++++++++++++++
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1 file changed, 37 insertions(+)
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--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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@@ -35,11 +35,17 @@
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#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
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#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
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#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
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+#define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1 0x1004
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+#define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1 0x1104
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+#define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1 0x2004
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+#define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1 0x2104
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#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
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#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
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#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
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#define RK3588_LANE_AGGREGATION BIT(2)
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+#define RK3588_RX_CMN_REFCLK_MODE_EN ((BIT(7) << 16) | BIT(7))
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+#define RK3588_RX_CMN_REFCLK_MODE_DIS (BIT(7) << 16)
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#define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16)
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#define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16)
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@@ -60,6 +66,7 @@ struct rockchip_p3phy_priv {
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int num_clks;
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int num_lanes;
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u32 lanes[4];
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+ u32 rx_cmn_refclk_mode[4];
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};
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struct rockchip_p3phy_ops {
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@@ -137,6 +144,19 @@ static int rockchip_p3phy_rk3588_init(st
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u8 mode = RK3588_LANE_AGGREGATION; /* default */
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int ret;
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+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1,
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+ priv->rx_cmn_refclk_mode[0] ? RK3588_RX_CMN_REFCLK_MODE_EN :
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+ RK3588_RX_CMN_REFCLK_MODE_DIS);
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+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1,
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+ priv->rx_cmn_refclk_mode[1] ? RK3588_RX_CMN_REFCLK_MODE_EN :
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+ RK3588_RX_CMN_REFCLK_MODE_DIS);
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+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1,
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+ priv->rx_cmn_refclk_mode[2] ? RK3588_RX_CMN_REFCLK_MODE_EN :
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+ RK3588_RX_CMN_REFCLK_MODE_DIS);
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+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1,
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+ priv->rx_cmn_refclk_mode[3] ? RK3588_RX_CMN_REFCLK_MODE_EN :
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+ RK3588_RX_CMN_REFCLK_MODE_DIS);
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+
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/* Deassert PCIe PMA output clamp mode */
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regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
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@@ -275,6 +295,23 @@ static int rockchip_p3phy_probe(struct p
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return priv->num_lanes;
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}
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+ ret = of_property_read_variable_u32_array(dev->of_node,
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+ "rockchip,rx-common-refclk-mode",
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+ priv->rx_cmn_refclk_mode, 1,
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+ ARRAY_SIZE(priv->rx_cmn_refclk_mode));
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+ /*
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+ * if no rockchip,rx-common-refclk-mode, assume enabled for all lanes in
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+ * order to be DT backwards compatible. (Since HW reset val is enabled.)
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+ */
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+ if (ret == -EINVAL) {
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+ for (int i = 0; i < ARRAY_SIZE(priv->rx_cmn_refclk_mode); i++)
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+ priv->rx_cmn_refclk_mode[i] = 1;
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+ } else if (ret < 0) {
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+ dev_err(dev, "failed to read rockchip,rx-common-refclk-mode property %d\n",
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+ ret);
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+ return ret;
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+ }
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+
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priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
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if (IS_ERR(priv->phy)) {
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dev_err(dev, "failed to create combphy\n");
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