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c7c0b7bc02
Reorder to start from 001. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/16149 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
128 lines
4.4 KiB
Diff
128 lines
4.4 KiB
Diff
From 8612169a05c5e979af033868b7a9b177e0f9fcdf Mon Sep 17 00:00:00 2001
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From: Dragan Simic <dsimic@manjaro.org>
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Date: Sat, 9 Mar 2024 05:25:06 +0100
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Subject: [PATCH] arm64: dts: rockchip: Add cache information to the SoC dtsi
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for RK356x
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Add missing cache information to the Rockchip RK356x SoC dtsi, to allow
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the userspace, which includes lscpu(1) that uses the virtual files provided
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by the kernel under the /sys/devices/system/cpu directory, to display the
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proper RK3566 and RK3568 cache information.
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Adding the cache information to the RK356x SoC dtsi also makes the following
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warning message in the kernel log go away:
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cacheinfo: Unable to detect cache hierarchy for CPU 0
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The cache parameters for the RK356x dtsi were obtained and partially derived
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by hand from the cache size and layout specifications found in the following
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datasheets and technical reference manuals:
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- Rockchip RK3566 datasheet, version 1.1
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- Rockchip RK3568 datasheet, version 1.3
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- ARM Cortex-A55 revision r1p0 TRM, version 0100-00
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- ARM DynamIQ Shared Unit revision r4p0 TRM, version 0400-02
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For future reference, here's a rather detailed summary of the documentation,
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which applies to both Rockchip RK3566 and RK3568 SoCs:
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- All caches employ the 64-byte cache line length
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- Each Cortex-A55 core has 32 KB of L1 4-way, set-associative instruction
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cache and 32 KB of L1 4-way, set-associative data cache
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- There are no L2 caches, which are per-core and private in Cortex-A55,
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because it belongs to the ARM DynamIQ IP core lineup
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- The entire SoC has 512 KB of unified L3 16-way, set-associative cache,
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which is shared among all four Cortex-A55 CPU cores
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- Cortex-A55 cores can be configured without private per-core L2 caches,
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in which case the shared L3 cache appears to them as an L2 cache; this
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is the case for the RK356x SoCs, so let's use "cache-level = <2>" to
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prevent the "huh, no L2 caches, but an L3 cache?" confusion among the
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users viewing the data presented to the userspace; another option could
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be to have additional 0 KB L2 caches defined, which may be technically
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correct, but would probably be even more confusing
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Helped-by: Anand Moon <linux.amoon@gmail.com>
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Tested-By: Diederik de Haas <didi.debian@cknow.org>
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Reviewed-by: Anand Moon <linux.amoon@gmail.com>
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Signed-off-by: Dragan Simic <dsimic@manjaro.org>
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Link: https://lore.kernel.org/r/2dee6dad8460b0c5f3b5da53cf55f735840efef1.1709957777.git.dsimic@manjaro.org
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 41 ++++++++++++++++++++++++
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1 file changed, 41 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -57,6 +57,13 @@
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#cooling-cells = <2>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <128>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <128>;
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+ next-level-cache = <&l3_cache>;
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};
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cpu1: cpu@100 {
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@@ -66,6 +73,13 @@
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#cooling-cells = <2>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <128>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <128>;
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+ next-level-cache = <&l3_cache>;
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};
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cpu2: cpu@200 {
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@@ -75,6 +89,13 @@
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#cooling-cells = <2>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <128>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <128>;
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+ next-level-cache = <&l3_cache>;
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};
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cpu3: cpu@300 {
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@@ -84,9 +105,29 @@
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#cooling-cells = <2>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <128>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <128>;
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+ next-level-cache = <&l3_cache>;
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};
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};
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+ /*
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+ * There are no private per-core L2 caches, but only the
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+ * L3 cache that appears to the CPU cores as L2 caches
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+ */
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+ l3_cache: l3-cache {
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+ compatible = "cache";
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+ cache-level = <2>;
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+ cache-unified;
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+ cache-size = <0x80000>;
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+ cache-line-size = <64>;
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+ cache-sets = <512>;
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+ };
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+
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cpu0_opp_table: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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