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6b681fd285
For all switch ports where the assigned SerDes is known, add the new pcs-handle to the dts. Leave the existing <sds> assignments to the PHYs as is because the driver has not yet been updated. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/20111 Signed-off-by: Robert Marko <robimarko@gmail.com>
51 lines
1.0 KiB
Plaintext
51 lines
1.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl9302_zyxel_xgs1210-12-common.dtsi"
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/ {
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compatible = "zyxel,xgs1210-12-a1", "realtek,rtl838x-soc";
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model = "Zyxel XGS1210-12 A1 Switch";
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};
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&mdio_bus0 {
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phy24: ethernet-phy@24 {
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reg = <24>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 8>;
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sds = < 6 >;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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phy25: ethernet-phy@25 {
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reg = <25>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <2 9>;
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sds = < 7 >;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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};
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&switch0 {
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ports {
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port@24 {
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reg = <24>;
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label = "lan9";
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pcs-handle = <&serdes6>;
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phy-handle = <&phy24>;
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phy-mode = "2500base-x";
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led-set = <1>;
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};
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port@25 {
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reg = <25>;
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label = "lan10";
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pcs-handle = <&serdes7>;
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phy-handle = <&phy25>;
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phy-mode = "2500base-x";
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led-set = <1>;
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};
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};
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};
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