mirror of
https://git.openwrt.org/openwrt/openwrt.git
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5c2eca676a
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.24
Removed upstreamed:
generic/backport-6.6/838-v6.9-leds-trigger-netdev-Fix-kernel-panic-on-interface-re.patch[1]
generic/backport-6.6/981-mtd-spinand-Add-support-for-5-byte-IDs.patch[2]
mediatek/patches-6.6/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch[3]
Removed:
ipq40xx/patches-6.6/110-mtd-limit-OTP-nvmem-to-non-nand-devices.patch[4]
All other patches automatically rebased.
1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.24&id=10f2af1af8ab8a7064f193446abd5579d3def7e3
2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.24&id=9c74507e6c4382d12a5e418742b81fd441f03313
3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.24&id=fe750e2744428be6aec7395b13df3b34381ce6b6
4. Acknowledgment to @DragonBlurp for pointing out the redundancy of this patch. dd78a59cd7
Build system: x86/64
Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Signed-off-by: John Audia <therealgraysky@proton.me>
110 lines
4.4 KiB
Diff
110 lines
4.4 KiB
Diff
From 0c5b5243ad55ae744e790ba90c5ad37a93bd1377 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Tue, 11 Oct 2022 23:38:45 +0200
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Subject: [PATCH] clk: qcom: ipq6018: workaround networking clock parenting
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Currently, networking clocks are only looked up by fw_name however,
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these are registered and setup by SSDK and are not available to the
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GCC driver at all, so work around that by providing a global name
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fallback.
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While we are here, provide global fallback for bias_pll_cc_clk and
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bias_pll_nss_noc_clk as well as these are fixed clocks also not available
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to the driver.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq6018.c | 39 +++++++++++++++++-----------------
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1 file changed, 19 insertions(+), 20 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq6018.c
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+++ b/drivers/clk/qcom/gcc-ipq6018.c
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@@ -360,7 +360,7 @@ static const struct freq_tbl ftbl_nss_pp
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static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
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{ .fw_name = "xo" },
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- { .fw_name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll4.clkr.hw },
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{ .hw = &nss_crypto_pll.clkr.hw },
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@@ -526,12 +526,12 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data
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gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
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{ .fw_name = "xo" },
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- { .fw_name = "uniphy0_gcc_rx_clk" },
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- { .fw_name = "uniphy0_gcc_tx_clk" },
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- { .fw_name = "uniphy1_gcc_rx_clk" },
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- { .fw_name = "uniphy1_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
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+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .fw_name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map
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@@ -573,12 +573,12 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data
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gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
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{ .fw_name = "xo" },
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- { .fw_name = "uniphy0_gcc_tx_clk" },
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- { .fw_name = "uniphy0_gcc_rx_clk" },
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- { .fw_name = "uniphy1_gcc_tx_clk" },
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- { .fw_name = "uniphy1_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
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+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .fw_name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map
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@@ -714,10 +714,10 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
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{ .fw_name = "xo" },
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- { .fw_name = "uniphy0_gcc_rx_clk" },
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- { .fw_name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .fw_name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
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@@ -750,10 +750,10 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
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{ .fw_name = "xo" },
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- { .fw_name = "uniphy0_gcc_tx_clk" },
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- { .fw_name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .fw_name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
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@@ -1899,12 +1899,11 @@ static const struct freq_tbl ftbl_ubi32_
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{ }
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};
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-static const struct clk_parent_data
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- gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
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+static const struct clk_parent_data gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
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{ .fw_name = "xo" },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll2.clkr.hw },
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- { .fw_name = "bias_pll_nss_noc_clk" },
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+ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
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};
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static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {
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