mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-11-22 04:56:15 +00:00
4c6e9a9943
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.30 Removed upstreamed: ipq806x/patches-6.6/130-mtd-rawnand-qcom-Fix-broken-misc_cmd_type-in-exec_op.patch[1] Manually rebased: generic/pending-6.6/760-net-core-add-optional-threading-for-backlog-processi.patch mediatek/patches-6.6/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.30&id=87fc30db0a2bb300de289dae7c5579cc27a3cbbd Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3, flogic/glinet_gl-mt6000 Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3, flogic/glinet_gl-mt6000 Signed-off-by: John Audia <therealgraysky@proton.me>
41 lines
1.3 KiB
Diff
41 lines
1.3 KiB
Diff
From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
|
|
From: Maso Huang <maso.huang@mediatek.com>
|
|
Date: Thu, 7 Sep 2023 10:54:37 +0800
|
|
Subject: [PATCH] arm64: dts: mt7986: add afe
|
|
|
|
---
|
|
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 23 +++++++++++
|
|
1 files changed, 23 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
|
@@ -202,6 +202,28 @@
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
+ afe: audio-controller@11210000 {
|
|
+ compatible = "mediatek,mt7986-afe";
|
|
+ reg = <0 0x11210000 0 0x9000>;
|
|
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
|
|
+ <&infracfg CLK_INFRA_AUD_26M_CK>,
|
|
+ <&infracfg CLK_INFRA_AUD_L_CK>,
|
|
+ <&infracfg CLK_INFRA_AUD_AUD_CK>,
|
|
+ <&infracfg CLK_INFRA_AUD_EG2_CK>;
|
|
+ clock-names = "aud_bus_ck",
|
|
+ "aud_26m_ck",
|
|
+ "aud_l_ck",
|
|
+ "aud_aud_ck",
|
|
+ "aud_eg2_ck";
|
|
+ assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
|
|
+ <&topckgen CLK_TOP_AUD_L_SEL>,
|
|
+ <&topckgen CLK_TOP_A_TUNER_SEL>;
|
|
+ assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
|
|
+ <&apmixedsys CLK_APMIXED_APLL2>,
|
|
+ <&topckgen CLK_TOP_APLL2_D4>;
|
|
+ };
|
|
+
|
|
pwm: pwm@10048000 {
|
|
compatible = "mediatek,mt7986-pwm";
|
|
reg = <0 0x10048000 0 0x1000>;
|