mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-11-22 04:56:15 +00:00
5b4bbd1097
Refresh patches and fix changed path for 32-bit mediatek boards 'arch/arm/dts' -> 'arch/arm/dts/mediatek' Signed-off-by: Daniel Golle <daniel@makrotopia.org>
28 lines
1.0 KiB
Diff
28 lines
1.0 KiB
Diff
--- a/drivers/crypto/inside-secure/safexcel.c
|
|
+++ b/drivers/crypto/inside-secure/safexcel.c
|
|
@@ -608,6 +608,14 @@ static int safexcel_hw_init(struct safex
|
|
val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
|
|
writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
|
|
}
|
|
+ /*
|
|
+ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3
|
|
+ */
|
|
+ else {
|
|
+ val = 0;
|
|
+ val |= EIP97_MST_CTRL_TX_MAX_CMD(4);
|
|
+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
|
|
+ }
|
|
|
|
/* Configure wr/rd cache values */
|
|
writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
|
|
--- a/drivers/crypto/inside-secure/safexcel.h
|
|
+++ b/drivers/crypto/inside-secure/safexcel.h
|
|
@@ -315,6 +315,7 @@
|
|
#define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
|
|
#define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
|
|
#define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
|
|
+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4)
|
|
#define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
|
|
#define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
|
|
#define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)
|