mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2025-10-12 13:37:18 +00:00
8b891001f6
- SoC : MediaTek MT7986AV, Quad-core 2.0 GHz ARM Cortex-A53 CPU
- RAM : DDR3 512 MiB (Micron MT41K256M16TW-107)
- Flash : SPI-NAND 128 MiB (Winbound W25N01GVZEIG)
- Ethernet : 6 ports
- LAN :
5x 10/100/1000 Mbps RJ-45 Port
- WAN :
1x 10/100/1000/2500 Mbps RJ-45 Port (MaxLinear GPY211B1VC-LN8A)
- LED : 19x LEDs (Green)
1x Power
1x Status (PWM-LED)
1x Debug (PWM-LED)
2x WiFi activity
10x Ethernet LAN activity
4x Ethernet WAN activity
- UART : 1x4 pin header on PCB [J1]
- arrangement : 3.3V, RX, TX, GND
- settings : 115200, 8n1
- Button : 3x (Reset, WPS, Power)
- WiFi : 2x
WiFi 6 2.4 Ghz + 5 Ghz (Mediatek MT7975N+MT7975PN)
- Socket :
1x Raspberry header 13x2
1x JTAG 10x2
1x USB-A (USB 3.0)
- Power : 12V DC, 3A
MAC addresses :
WLAN: 00:0A:52:xx:xx:xx (Factory, 0x6)
LAN: 00:0A:52:xx:xx:xx (Factory, 0x24)
WAN: 00:0A:52:xx:xx:xx (Factory, 0x2a)
Flash instruction through LuCI:
This device is flashed OpenWRT base firmware with this target.
The LuCI webpage is integrated in default for upgrading.
Flash instruction through u-boot:
1. Prepare the TFTP server on PC.
2. Connect uart to PC, select "2. Upgrade firmware" in u-boot menu.
3. Select "0 - TFTP client (Default)", input client IP, server IP, IP netmask, flashed bin file path
4. Wait about 20 seconds to complete flashing
Signed-off-by: Elwin Huang <s09289728096@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20071
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
428 lines
7.7 KiB
Plaintext
428 lines
7.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2025 AsiaRF Co., Ltd
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* Author: Elwin Huang <elwin@asiarf.com>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include "mt7986a.dtsi"
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/ {
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model = "AsiaRF AP7986-003";
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compatible = "asiarf,ap7986-003", "mediatek,mt7986a-rfb";
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aliases {
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serial0 = &uart0;
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led-boot = &led_status_green;
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led-failsafe = &led_status_green;
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led-running = &led_status_green;
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led-upgrade = &led_status_green;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@40000000 {
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reg = <0 0x40000000 0 0x20000000>;
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device_type = "memory";
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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};
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};
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pwm-leds {
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compatible = "pwm-leds";
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led_status_green: led-0 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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pwms = <&pwm 0 10000>;
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active-low;
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};
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led-1 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DEBUG;
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pwms = <&pwm 1 10000>;
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linux,default-trigger = "pattern";
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led-pattern = <0 1000 255 1000>;
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active-low;
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};
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_5v: regulator-5v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "2500base-x";
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nvmem-cells = <&macaddr_factory_24>;
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nvmem-cell-names = "mac-address";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-handle = <&phy6>;
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phy-mode = "2500base-x";
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nvmem-cells = <&macaddr_factory_2a>;
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nvmem-cell-names = "mac-address";
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};
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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phy6: phy@6 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <6>;
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reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
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reset-deassert-us = <20000>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&pio>;
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interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
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};
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switch: switch@1f {
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compatible = "mediatek,mt7531";
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reg = <31>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&pio>;
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interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
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reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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};
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port@4 {
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reg = <4>;
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label = "lan5";
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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};
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&wifi {
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pinctrl-names = "default", "dbdc";
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pinctrl-0 = <&wf_2g_5g_pins>;
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pinctrl-1 = <&wf_dbdc_pins>;
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nvmem-cells = <&eeprom_factory_0>;
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nvmem-cell-names = "eeprom";
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status = "okay";
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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status = "okay";
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};
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&pcie_phy {
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status = "okay";
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};
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&pio {
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pcie_pins: pcie-pins {
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mux {
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function = "pcie";
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groups = "pcie_clk", "pcie_wake", "pcie_pereset";
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};
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};
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pwm_pins: pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0", "pwm1_0";
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};
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};
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spic1_pins: spi-pins-23-to-26 {
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mux {
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function = "spi";
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groups = "spi1_1";
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};
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};
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spic2_pins: spi-flash-pins-29-to-32 {
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mux {
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function = "spi";
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groups = "spi1_2";
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};
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};
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spi_flash_pins: spi-flash-pins-33-to-38 {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-disable; /* bias-disable */
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};
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conf-pd {
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pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-disable; /* bias-disable */
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};
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};
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wf_2g_5g_pins: wf_2g_5g-pins {
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mux {
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function = "wifi";
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groups = "wf_2g", "wf_5g";
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};
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conf {
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pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
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"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
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"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
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"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
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"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
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"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
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"WF1_TOP_CLK", "WF1_TOP_DATA";
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drive-strength = <MTK_DRIVE_4mA>;
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};
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};
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wf_dbdc_pins: wf_dbdc-pins {
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mux {
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function = "wifi";
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groups = "wf_dbdc";
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};
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conf {
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pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
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"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
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"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
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"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
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"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
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"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
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"WF1_TOP_CLK", "WF1_TOP_DATA";
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drive-strength = <MTK_DRIVE_4mA>;
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};
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};
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i2c_pins: i2c-pins {
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mux {
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function = "i2c";
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groups = "i2c";
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};
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_flash_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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spi_nand@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-nand";
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reg = <1>;
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spi-max-frequency = <52000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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mediatek,nmbm;
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mediatek,bmt-max-ratio = <1>;
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mediatek,bmt-max-reserved-blocks = <64>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "BL2";
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reg = <0x00000 0x0100000>;
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read-only;
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};
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partition@100000 {
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label = "u-boot-env";
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reg = <0x0100000 0x0080000>;
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};
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partition@180000 {
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label = "Factory";
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reg = <0x0180000 0x0200000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0x1000>;
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};
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macaddr_factory_24: macaddr@24 {
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reg = <0x24 0x6>;
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};
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macaddr_factory_2a: macaddr@2a {
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reg = <0x2a 0x6>;
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};
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};
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};
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partition@380000 {
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label = "FIP";
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reg = <0x0380000 0x0200000>;
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};
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partition@580000 {
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label = "ubi";
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reg = <0x0580000 0x4000000>; // 64MB
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};
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partition@4580000 {
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label = "User_data";
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reg = <0x4580000 0x3280000>;
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};
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};
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};
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spic1_pins &spic2_pins>;
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cs-gpios = <&pio 26 GPIO_ACTIVE_LOW>, <&pio 32 GPIO_ACTIVE_LOW>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&ssusb {
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phys = <&u3port0 PHY_TYPE_USB3>,
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<&u2port1 PHY_TYPE_USB2>;
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vusb33-supply = <®_3p3v>;
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vbus-supply = <®_5v>;
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status = "okay";
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};
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&usb_phy {
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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&trng {
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status = "okay";
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};
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&crypto {
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status = "okay";
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm_pins>;
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status = "okay";
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};
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