openwrt/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax-v2.dts

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

#include "mt7981b.dtsi"

/ {
	model = "ZBT Z8102AX V2";
	compatible = "zbtlink,zbt-z8102ax-v2", "mediatek,mt7981";

	aliases {
		serial0 = &uart0;
		led-boot = &led_status_red;
		led-failsafe = &led_status_red;
		led-running = &led_status_green;
		led-upgrade = &led_status_green;
		label-mac-device = &gmac0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
	};

	gpio-keys {
		compatible = "gpio-keys";

		reset {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
		};

		wps {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
		};
		
	};

	leds {
		compatible = "gpio-leds";

		led_status_red: red {
			gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_RED>;
			function = LED_FUNCTION_STATUS;
		};

		led_status_green: green {
			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_STATUS;
		};
		
		led_status_blue: blue {
			gpios = <&pio 11 GPIO_ACTIVE_LOW>;
			color = <LED_COLOR_ID_BLUE>;
			function = LED_FUNCTION_STATUS;
		};
		
		led_status_5g1: 5g1 {
			gpios = <&pio 8 GPIO_ACTIVE_LOW>;
			color = <LED_COLOR_ID_BLUE>;
			function = LED_FUNCTION_USB;
			function-enumerator = <0>;
		};
		
		led_status_5g2: 5g2 {
			gpios = <&pio 13 GPIO_ACTIVE_LOW>;
			color = <LED_COLOR_ID_BLUE>;
			function = LED_FUNCTION_USB;
			function-enumerator = <1>;
		};
	};

	watchdog {
		compatible = "linux,wdt-gpio";
		gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
		hw_algo = "toggle";
		hw_margin_ms = <1000>;
	};

	gpio-export {
		compatible = "gpio-export";
		#size-cells = <0>;

		pcie {
			gpio-export,name = "pcie_power";
			gpio-export,output = <1>;
			gpios = <&pio 3 GPIO_ACTIVE_HIGH>;
		};

		5g1 {
			gpio-export,name = "5g1";
			gpio-export,output = <1>;
			gpios = <&pio 4 GPIO_ACTIVE_HIGH>;
		};

		5g2 {
			gpio-export,name = "5g2";
			gpio-export,output = <1>;
			gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
		};

		sim1 {
			gpio-export,name = "sim1";
			gpio-export,output = <0>;
			gpios = <&pio 6 GPIO_ACTIVE_LOW>;
		};

		sim2 {
			gpio-export,name = "sim2";
			gpio-export,output = <0>;
			gpios = <&pio 7 GPIO_ACTIVE_LOW>;
		};
	};
};

&eth {
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "2500base-x";
		nvmem-cell-names = "mac-address";

		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
		};
	};
	
	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-mode = "gmii";
		phy-handle = <&int_gbe_phy>;
		nvmem-cell-names = "mac-address";
		nvmem-cells = <&macaddr_factory_02a>;
	};
};

&mdio_bus {
	switch: switch@1f {
		compatible = "mediatek,mt7531";
		reg = <31>;
		reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&pio>;
		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_flash_pins>;
	status = "okay";

	spi_nand@0 {
		compatible = "spi-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;

		spi-max-frequency = <52000000>;
		spi-tx-buswidth = <4>;
		spi-rx-buswidth = <4>;

		mediatek,nmbm;
		mediatek,bmt-max-ratio = <1>;
		mediatek,bmt-max-reserved-blocks = <64>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "bl2";
				reg = <0x0000000 0x0100000>;
				read-only;
			};

			partition@100000 {
				label = "u-boot-env";
				reg = <0x0100000 0x0080000>;
			};

			factory: partition@180000 {
				label = "Factory";
				reg = <0x0180000 0x0200000>;
				read-only;
			};

			partition@380000 {
				label = "FIP";
				reg = <0x0380000 0x0200000>;
				read-only;
			};

			nand_rootfs: partition@580000 {
				label = "ubi";
				reg = <0x0580000 0x7220000>;
			};
		};
	};
};

&switch {
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			label = "lan1";
			nvmem-cell-names = "mac-address";
			nvmem-cells = <&macaddr_factory_004>;
		};

		port@1 {
			reg = <1>;
			label = "lan2";
			nvmem-cell-names = "mac-address";
			nvmem-cells = <&macaddr_factory_004>;
		};

		port@2 {
			reg = <2>;
			label = "lan3";
			nvmem-cell-names = "mac-address";
			nvmem-cells = <&macaddr_factory_004>;
		};

		port@3 {
			reg = <3>;
			label = "lan4";
			nvmem-cell-names = "mac-address";
			nvmem-cells = <&macaddr_factory_004>;
		};

		port@6 {
			reg = <6>;
			label = "cpu";
			ethernet = <&gmac0>;
			phy-mode = "2500base-x";

			fixed-link {
				speed = <2500>;
				full-duplex;
				pause;
			};
		};
	};
};

&pio {
	gpio-line-names = 
			"wps",
			"reset",
			"watchdog",
			"pcie",
			"5g1",
			"5g2",
			"sim1",
			"sim2",
			"5g1_status",
			"red_status",
			"green_status",
			"blue_status",
			"",
			"5g2_status";

	spi0_flash_pins: spi0-pins {
		mux {
			function = "spi";
			groups = "spi0", "spi0_wp_hold";
		};

		conf-pu {
			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
			drive-strength = <8>;
			mediatek,pull-up-adv = <0>; /* bias-disable */
		};

		conf-pd {
			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
			drive-strength = <8>;
			mediatek,pull-up-adv = <0>; /* bias-disable */
		};
	};
};

&uart0 {
	status = "okay";
};

&watchdog {
	status = "okay";
};

&usb_phy {
	status = "okay";
};

&xhci {
	status = "okay";
};

&wifi {
	status = "okay";
        nvmem-cells = <&eeprom_factory>;
        nvmem-cell-names = "eeprom";
};

&factory {
	compatible = "nvmem-cells";
	#address-cells = <1>;
	#size-cells = <1>;

	macaddr_factory_004: macaddr@004 {
		reg = <0x004 0x6>;
	};
	macaddr_factory_02a: macaddr@02a {
		reg = <0x02a 0x6>;
	};
        eeprom_factory: eeprom@0 {
		reg = <0x0 0x1000>;
	};
};