mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2025-09-21 13:39:22 +00:00
73e04e2464
- SoC : MediaTek MT7622A, dual-core 1.35 Ghz ARM Cortex-A53 CPU
- RAM : DDR3 512 MiB (Nanya NT5CC256M16ER-EKI)
- Flash : SPI-NAND 128 MiB (Winbond W25N01GVZEIG)
- Ethernet : 5 port Switch
- LAN :
4x 10/100/1000 Mbps RJ-45 Port
- WAN :
1x 10/100/1000 Mbps RJ-45 Port
- LED : 10x LEDs
1x Power (Blue, GPIO)
1x WiFi (Green, GPIO)
2x MiniPCIe (Orange)
1x M.2 B Key (Red)
5x Ethernet activity (White)
- UART : 1x4 pin header on PCB [J19]
- arrangement : 3.3V, TX, RX, GND
- settings : 115200, 8n1
- Button : 2x (Reset, WPS)
- GPS : 1x (Quectel L76-L)
- WiFi : 2x
WiFi 4 (MediaTek MT7622A)
WiFI HaLow (AsiaRF MM610X-001)
- BT : BT 4.2/BLE 5.0 (MediaTek MT7622A)
- Socket :
2x MiniPCIe (PCIe Gen2 + USB 2.0) with extra SPI interface (NI)
1x M.2 B key (USB 3.0)
1x SIM Card
1x USB-A (USB 2.0)
- Power : 12V DC, 1A
MAC addresses :
WLAN: 00:0A:52:xx:xx:xx (Factory, 0x6)
LAN: 00:0A:52:xx:xx:xx (Factory, 0x7fff4)
WAN: 00:0A:52:xx:xx:xx (Factory, 0x7fffa)
Note: To use SPI interface on mPCIe slot, weld 4x 0402 0R resistors on [R832-835] or [R960-963]
mPCIe mapping:
45# - SPI_CLK
47# - SPI_MISO
49# - SPI_MOSI
51# - SPI_CSN
Flash instruction through LuCI:
This device is flashed OpenWRT base firmware with this target.
The LuCI webpage is integrated in default for upgrading.
Flash instruction through u-boot:
1. Prepare the TFTP server on PC.
2. Connect uart to PC, select "2. System Load Linux Kernel then write to Flash via TFTP." in u-boot menu.
3. input flashed bin file path, server IP, client IP
4. Wait about 20 seconds to complete flashing
Signed-off-by: Elwin Huang <s09289728096@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19962
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
516 lines
8.7 KiB
Plaintext
516 lines
8.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2025 AsiaRF Co., Ltd
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* Author: Elwin Huang <elwin@asiarf.com>
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*/
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/dts-v1/;
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#include "mt7622.dtsi"
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#include "mt6380.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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model = "AsiaRF AP7622 WH1";
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compatible = "asiarf,ap7622-wh1", "mediatek,mt7622";
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aliases {
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serial0 = &uart0;
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
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};
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cpus {
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cpu@0 {
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proc-supply = <&mt6380_vcpu_reg>;
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sram-supply = <&mt6380_vm_reg>;
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};
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cpu@1 {
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proc-supply = <&mt6380_vcpu_reg>;
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sram-supply = <&mt6380_vm_reg>;
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};
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};
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mmc1_pwrseq: mmc1_pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&pio 97 GPIO_ACTIVE_LOW>;
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post-power-on-delay-ms = <200>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&pio 102 GPIO_ACTIVE_LOW>;
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};
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};
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memory@40000000 {
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reg = <0 0x40000000 0 0x20000000>;// 512MiB
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device_type = "memory";
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_5v: regulator-5v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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gpio-leds {
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compatible = "gpio-leds";
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status = "okay";
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led_power: power {
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_POWER;
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gpios = <&pio 101 GPIO_ACTIVE_HIGH>;
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};
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wlan {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_WLAN;
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gpios = <&pio 85 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0tpt";
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};
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};
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};
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&bch {
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status = "okay";
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};
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&rtc {
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status = "disabled";
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};
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ð {
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pinctrl-names = "default";
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pinctrl-0 = <ð_pins>;
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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nvmem-cells = <&macaddr_factory_7fff4>;
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nvmem-cell-names = "mac-address";
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reg = <0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@1f {
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compatible = "mediatek,mt7531";
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reg = <31>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&pio>;
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interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
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reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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};
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port@4 {
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reg = <4>;
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label = "wan";
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nvmem-cells = <&macaddr_factory_7fffa>;
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nvmem-cell-names = "mac-address";
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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};
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&mmc1 {
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&sd0_pins_default>;
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pinctrl-1 = <&sd0_pins_uhs>;
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status = "okay";
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bus-width = <4>;
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max-frequency = <50000000>;
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cap-sd-highspeed;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_3p3v>;
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assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
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cap-mmc-highspeed;
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cap-sdio-irq;
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non-removable;
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disable-wp;
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drv-type = <2>;
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mmc-pwrseq = <&mmc1_pwrseq>;
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#address-cells = <1>;
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#size-cells = <0>;
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mm6108_sdio@0 {
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compatible = "morse,mm610x";
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reset-gpios = <&pio 97 GPIO_ACTIVE_HIGH>;
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power-gpios = <&pio 98 GPIO_ACTIVE_HIGH>,
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<&pio 99 GPIO_ACTIVE_HIGH>;
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status = "okay";
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reg = <2>;
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bus-width = <4>;
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};
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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};
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&pcie1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_pins>;
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status = "okay";
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};
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&pio {
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eth_pins: eth-pins {
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mux {
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function = "eth";
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groups = "mdc_mdio", "rgmii_via_gmac2";
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};
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};
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pcie0_pins: pcie0-pins {
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mux {
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function = "pcie";
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groups = "pcie0_pad_perst",
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"pcie0_1_waken",
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"pcie0_1_clkreq";
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};
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};
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pcie1_pins: pcie1-pins {
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mux {
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function = "pcie";
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groups = "pcie1_pad_perst",
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"pcie1_0_waken",
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"pcie1_0_clkreq";
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};
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};
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pmic_bus_pins: pmic-bus-pins {
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mux {
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function = "pmic";
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groups = "pmic_bus";
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};
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};
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wled_pins: wled-pins {
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mux {
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function = "led";
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groups = "wled";
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};
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};
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sd0_pins_default: sd0-pins-default {
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mux {
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function = "sd";
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groups = "sd_0";
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};
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/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
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* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
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* DAT2, DAT3, CMD, CLK for SD respectively.
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*/
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conf-cmd-data {
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pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
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"I2S2_IN","I2S4_OUT";
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input-enable;
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drive-strength = <8>;
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bias-pull-up;
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};
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conf-clk {
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pins = "I2S3_OUT";
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drive-strength = <12>;
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bias-pull-down;
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};
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conf-cd {
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pins = "TXD3";
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bias-pull-up;
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};
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};
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sd0_pins_uhs: sd0-pins-uhs {
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mux {
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function = "sd";
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groups = "sd_0";
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};
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conf-cmd-data {
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pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
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"I2S2_IN","I2S4_OUT";
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input-enable;
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bias-pull-up;
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};
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conf-clk {
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pins = "I2S3_OUT";
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bias-pull-down;
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};
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};
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/* Serial NAND is shared pin with SPI-NOR */
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serial_nand_pins: serial-nand-pins {
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mux {
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function = "flash";
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groups = "snfi";
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};
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};
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spic0_pins: spic0-pins {
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mux {
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function = "spi";
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groups = "spic0_0";
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};
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};
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spic1_pins: spic1-pins {
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mux {
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function = "spi";
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groups = "spic1_0";
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};
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};
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uart0_pins: uart0-pins {
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mux {
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function = "uart";
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groups = "uart0_0_tx_rx";
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};
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};
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uart2_pins: uart2-pins {
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mux {
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function = "uart";
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groups = "uart2_1_tx_rx";
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};
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};
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watchdog_pins: watchdog-pins {
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mux {
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function = "watchdog";
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groups = "watchdog";
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};
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};
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};
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&pwrap {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_bus_pins>;
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status = "okay";
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};
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&snfi {
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pinctrl-names = "default";
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pinctrl-0 = <&serial_nand_pins>;
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status = "okay";
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flash@0 {
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compatible = "spi-nand";
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mediatek,bmt-table-size = <0x1000>;
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mediatek,bmt-v2;
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nand-ecc-engine = <&snfi>;
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Preloader";
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reg = <0x00000 0x0080000>;
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read-only;
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};
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partition@80000 {
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label = "ATF";
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reg = <0x80000 0x0040000>;
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read-only;
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};
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partition@c0000 {
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label = "Bootloader";
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reg = <0xc0000 0x0080000>;
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read-only;
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};
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partition@140000 {
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label = "Config";
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reg = <0x140000 0x0080000>;
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};
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partition@1c0000 {
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label = "Factory";
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reg = <0x1c0000 0x0100000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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factory_eeprom: eeprom@0 {
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reg = <0x0 0x5000>;
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};
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macaddr_factory_7fff4: macaddr@7fff4 {
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reg = <0x7fff4 0x6>;
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};
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macaddr_factory_7fffa: macaddr@7fffa {
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reg = <0x7fffa 0x6>;
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};
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};
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};
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partition@2c0000 {
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label = "firmware";
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reg = <0x2c0000 0x2000000>;// 32 MiB
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x0 0x0800000>;
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};
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partition@600000 {
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label = "ubi";
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reg = <0x800000 0x1800000>;
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};
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};
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partition@22c0000 {
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label = "User_data";
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reg = <0x22c0000 0x5300000>;
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};
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};
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spic0_pins>;
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status = "okay";
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spic1_pins>;
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status = "okay";
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};
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&ssusb {
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vusb33-supply = <®_3p3v>;
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vbus-supply = <®_5v>;
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status = "okay";
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};
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&u3phy {
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status = "okay";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "okay";
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};
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&watchdog {
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pinctrl-names = "default";
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pinctrl-0 = <&watchdog_pins>;
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status = "okay";
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};
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&wmac {
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nvmem-cells = <&factory_eeprom>;
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nvmem-cell-names = "eeprom";
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status = "okay";
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};
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