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5f307b29cd
Add a set of upstream patches for the imx8m{m,n,p} based Venice
boards.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Link: https://github.com/openwrt/openwrt/pull/15736
Signed-off-by: Robert Marko <robimarko@gmail.com>
35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From e5bc89e60590581b0d31e8c6c6361c6caf5583bb Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Tue, 21 Nov 2023 11:12:24 -0800
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Subject: [PATCH 407/413] 6.9: arm64: dts: imx8mm-venice-gw7901: add digital
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I/O direction control GPIO's
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The GW7901 has GPIO's to configure the direction of its isolated
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digital I/O signals. Add the GPIO pinmux and line names.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
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+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
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@@ -319,7 +319,7 @@
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&gpio4 {
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gpio-line-names = "", "", "", "",
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- "", "", "uart3_rs232#", "uart3_rs422#",
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+ "dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#",
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"uart3_rs485#", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
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@@ -842,6 +842,8 @@
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pinctrl_hog: hoggrp {
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fsl,pins = <
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+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIG1_CTL */
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+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000041 /* DIG2_CTL */
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MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
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MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
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MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
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