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c5e359a236
Updating the spi-qpic-snand driver with the latest patches sent upstream and remove custom patches. These patches add error handling fixes, use of right read location in read ops, removal of unused variable, ability to read user config and nand chip requirements, and support for 8bits ECC strength. Tested on: Gl.iNet GL-B3000 & Linksys MR5500, MX2000, MX5500, SPNMX56 Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/18723 Signed-off-by: Robert Marko <robimarko@gmail.com>
71 lines
2.5 KiB
Diff
71 lines
2.5 KiB
Diff
From: Gabor Juhos <j4g8y7@gmail.com>
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Date: Fri, 02 May 2025 21:31:16 +0200
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Subject: [PATCH next 1/2] mtd: nand: qpic-common: add defines for ECC_MODE
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values
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Add defines for the values of the ECC_MODE field of the NAND_DEV0_ECC_CFG
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register and change both the 'qcom-nandc' and 'spi-qpic-snand' drivers to
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use those instead of magic numbers.
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No functional changes. This is in preparation for adding 8 bit ECC strength
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support for the 'spi-qpic-snand' driver.
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Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
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---
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drivers/mtd/nand/raw/qcom_nandc.c | 6 +++---
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drivers/spi/spi-qpic-snand.c | 2 +-
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include/linux/mtd/nand-qpic-common.h | 2 ++
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3 files changed, 6 insertions(+), 4 deletions(-)
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--- a/drivers/mtd/nand/raw/qcom_nandc.c
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+++ b/drivers/mtd/nand/raw/qcom_nandc.c
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@@ -1379,7 +1379,7 @@ static int qcom_nand_attach_chip(struct
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struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
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int cwperpage, bad_block_byte, ret;
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bool wide_bus;
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- int ecc_mode = 1;
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+ int ecc_mode = ECC_MODE_8BIT;
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/* controller only supports 512 bytes data steps */
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ecc->size = NANDC_STEP_SIZE;
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@@ -1400,7 +1400,7 @@ static int qcom_nand_attach_chip(struct
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if (ecc->strength >= 8) {
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/* 8 bit ECC defaults to BCH ECC on all platforms */
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host->bch_enabled = true;
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- ecc_mode = 1;
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+ ecc_mode = ECC_MODE_8BIT;
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if (wide_bus) {
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host->ecc_bytes_hw = 14;
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@@ -1420,7 +1420,7 @@ static int qcom_nand_attach_chip(struct
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if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
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/* BCH */
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host->bch_enabled = true;
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- ecc_mode = 0;
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+ ecc_mode = ECC_MODE_4BIT;
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if (wide_bus) {
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host->ecc_bytes_hw = 8;
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--- a/drivers/spi/spi-qpic-snand.c
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+++ b/drivers/spi/spi-qpic-snand.c
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@@ -349,7 +349,7 @@ static int qcom_spi_ecc_init_ctx_pipelin
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FIELD_PREP(ECC_SW_RESET, 0) |
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FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
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FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
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- FIELD_PREP(ECC_MODE_MASK, 0) |
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+ FIELD_PREP(ECC_MODE_MASK, ECC_MODE_4BIT) |
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FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
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ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS;
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--- a/include/linux/mtd/nand-qpic-common.h
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+++ b/include/linux/mtd/nand-qpic-common.h
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@@ -101,6 +101,8 @@
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#define ECC_SW_RESET BIT(1)
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#define ECC_MODE 4
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#define ECC_MODE_MASK GENMASK(5, 4)
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+#define ECC_MODE_4BIT 0
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+#define ECC_MODE_8BIT 1
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#define ECC_PARITY_SIZE_BYTES_BCH 8
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#define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8)
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#define ECC_NUM_DATA_BYTES 16
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