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4d81f40d63
Two patches declared as accepted in v6.13 were already accepted for
v6.12. Fix filenames and order of patches applied.
Reported-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Fixes: 8cc049cec2 ("generic: phy: aquantia: move accepted patches to backport-6.6")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
108 lines
3.7 KiB
Diff
108 lines
3.7 KiB
Diff
From a2e1ba275eae96a8171deb19e9c7c2f5978fee7b Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Fri, 4 Oct 2024 17:18:16 +0100
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Subject: [PATCH] net: phy: aquantia: allow forcing order of MDI pairs
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Despite supporting Auto MDI-X, it looks like Aquantia only supports
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swapping pair (1,2) with pair (3,6) like it used to be for MDI-X on
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100MBit/s networks.
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When all 4 pairs are in use (for 1000MBit/s or faster) the link does not
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come up with pair order is not configured correctly, either using
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MDI_CFG pin or using the "PMA Receive Reserved Vendor Provisioning 1"
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register.
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Normally, the order of MDI pairs being either ABCD or DCBA is configured
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by pulling the MDI_CFG pin.
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However, some hardware designs require overriding the value configured
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by that bootstrap pin. The PHY allows doing that by setting a bit in
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"PMA Receive Reserved Vendor Provisioning 1" register which allows
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ignoring the state of the MDI_CFG pin and another bit configuring
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whether the order of MDI pairs should be normal (ABCD) or reverse
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(DCBA). Pair polarity is not affected and remains identical in both
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settings.
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Introduce property "marvell,mdi-cfg-order" which allows forcing either
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normal or reverse order of the MDI pairs from DT.
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If the property isn't present, the behavior is unchanged and MDI pair
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order configuration is untouched (ie. either the result of MDI_CFG pin
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pull-up/pull-down, or pair order override already configured by the
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bootloader before Linux is started).
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Forcing normal pair order is required on the Adtran SDG-8733A Wi-Fi 7
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residential gateway.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Link: https://patch.msgid.link/9ed760ff87d5fc456f31e407ead548bbb754497d.1728058550.git.daniel@makrotopia.org
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/phy/aquantia/aquantia_main.c | 33 ++++++++++++++++++++++++
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1 file changed, 33 insertions(+)
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--- a/drivers/net/phy/aquantia/aquantia_main.c
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+++ b/drivers/net/phy/aquantia/aquantia_main.c
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@@ -11,6 +11,7 @@
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/bitfield.h>
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+#include <linux/of.h>
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#include <linux/phy.h>
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#include "aquantia.h"
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@@ -70,6 +71,11 @@
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#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
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#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
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+#define PMAPMD_RSVD_VEND_PROV 0xe400
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+#define PMAPMD_RSVD_VEND_PROV_MDI_CONF GENMASK(1, 0)
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+#define PMAPMD_RSVD_VEND_PROV_MDI_REVERSE BIT(0)
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+#define PMAPMD_RSVD_VEND_PROV_MDI_FORCE BIT(1)
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+
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#define MDIO_AN_RX_LP_STAT1 0xe820
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#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
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#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
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@@ -497,6 +503,29 @@ static int aqr107_wait_processor_intensi
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return 0;
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}
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+static int aqr107_config_mdi(struct phy_device *phydev)
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+{
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+ struct device_node *np = phydev->mdio.dev.of_node;
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+ u32 mdi_conf;
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+ int ret;
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+
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+ ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf);
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+
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+ /* Do nothing in case property "marvell,mdi-cfg-order" is not present */
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+ if (ret == -ENOENT)
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+ return 0;
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+
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+ if (ret)
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+ return ret;
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+
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+ if (mdi_conf & ~PMAPMD_RSVD_VEND_PROV_MDI_REVERSE)
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+ return -EINVAL;
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+
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+ return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_RSVD_VEND_PROV,
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+ PMAPMD_RSVD_VEND_PROV_MDI_CONF,
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+ mdi_conf | PMAPMD_RSVD_VEND_PROV_MDI_FORCE);
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+}
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+
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static int aqr107_config_init(struct phy_device *phydev)
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{
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struct aqr107_priv *priv = phydev->priv;
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@@ -535,6 +564,10 @@ static int aqr107_config_init(struct phy
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if (ret)
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return ret;
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+ ret = aqr107_config_mdi(phydev);
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+ if (ret)
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+ return ret;
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+
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/* Restore LED polarity state after reset */
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for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) {
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ret = aqr_phy_led_active_low_set(phydev, led_active_low, true);
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