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fe9d2ccbc3
Move accepted patches to backport folder, re-add previously removed patch
which caused havoc on MT7621 and add the (still pending) fix.
Fixes: d40691a5fb ("generic: 6.1, 6.6: mt7530: import pending patches")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
258 lines
8.4 KiB
Diff
258 lines
8.4 KiB
Diff
From 3ccf67597d35c06a7319e407b1c42f78a7966779 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Mon, 22 Apr 2024 10:15:13 +0300
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Subject: [PATCH 06/15] net: dsa: mt7530: refactor MT7530_HWTRAP and
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MT7530_MHWTRAP
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The MT7530_HWTRAP and MT7530_MHWTRAP registers are on MT7530 and MT7531.
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It's called hardware trap on MT7530, software trap on MT7531. That's
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because some bits of the trap on MT7530 cannot be modified by software
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whilst all bits of the trap on MT7531 can. Rename the definitions for them
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to MT753X_TRAP and MT753X_MTRAP. Add MT7530 and MT7531 prefixes to the
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definitions specific to the switch model.
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Remove the extra parentheses from MT7530_XTAL_40MHZ and MT7530_XTAL_20MHZ.
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Rename MHWTRAP_PHY0_SEL, MHWTRAP_MANUAL, and MHWTRAP_PHY_ACCESS to be on
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par with the "MT7621 Giga Switch Programming Guide v0.3" document.
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Make an enumaration for the XTAL frequency. Set the data type of the xtal
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variable on mt7531_pll_setup() to it.
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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---
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drivers/net/dsa/mt7530.c | 59 ++++++++++++++++++++--------------------
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drivers/net/dsa/mt7530.h | 50 ++++++++++++++++------------------
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2 files changed, 54 insertions(+), 55 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -417,23 +417,23 @@ mt7530_setup_port6(struct dsa_switch *ds
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mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
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- xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
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+ xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK;
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- if (xtal == HWTRAP_XTAL_25MHZ)
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+ if (xtal == MT7530_XTAL_25MHZ)
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ssc_delta = 0x57;
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else
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ssc_delta = 0x87;
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if (priv->id == ID_MT7621) {
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/* PLL frequency: 125MHz: 1.0GBit */
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- if (xtal == HWTRAP_XTAL_40MHZ)
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+ if (xtal == MT7530_XTAL_40MHZ)
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ncpo1 = 0x0640;
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- if (xtal == HWTRAP_XTAL_25MHZ)
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+ if (xtal == MT7530_XTAL_25MHZ)
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ncpo1 = 0x0a00;
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} else { /* PLL frequency: 250MHz: 2.0Gbit */
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- if (xtal == HWTRAP_XTAL_40MHZ)
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+ if (xtal == MT7530_XTAL_40MHZ)
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ncpo1 = 0x0c80;
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- if (xtal == HWTRAP_XTAL_25MHZ)
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+ if (xtal == MT7530_XTAL_25MHZ)
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ncpo1 = 0x1400;
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}
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@@ -456,19 +456,20 @@ mt7530_setup_port6(struct dsa_switch *ds
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static void
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mt7531_pll_setup(struct mt7530_priv *priv)
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{
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+ enum mt7531_xtal_fsel xtal;
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u32 top_sig;
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u32 hwstrap;
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- u32 xtal;
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u32 val;
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val = mt7530_read(priv, MT7531_CREV);
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top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
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- hwstrap = mt7530_read(priv, MT7531_HWTRAP);
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+ hwstrap = mt7530_read(priv, MT753X_TRAP);
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if ((val & CHIP_REV_M) > 0)
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- xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
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- HWTRAP_XTAL_FSEL_25MHZ;
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+ xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ :
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+ MT7531_XTAL_FSEL_25MHZ;
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else
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- xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
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+ xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ :
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+ MT7531_XTAL_FSEL_40MHZ;
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/* Step 1 : Disable MT7531 COREPLL */
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val = mt7530_read(priv, MT7531_PLLGP_EN);
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@@ -497,13 +498,13 @@ mt7531_pll_setup(struct mt7530_priv *pri
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usleep_range(25, 35);
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switch (xtal) {
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- case HWTRAP_XTAL_FSEL_25MHZ:
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+ case MT7531_XTAL_FSEL_25MHZ:
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val = mt7530_read(priv, MT7531_PLLGP_CR0);
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val &= ~RG_COREPLL_SDM_PCW_M;
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val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
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mt7530_write(priv, MT7531_PLLGP_CR0, val);
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break;
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- case HWTRAP_XTAL_FSEL_40MHZ:
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+ case MT7531_XTAL_FSEL_40MHZ:
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val = mt7530_read(priv, MT7531_PLLGP_CR0);
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val &= ~RG_COREPLL_SDM_PCW_M;
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val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
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@@ -877,20 +878,20 @@ static void mt7530_setup_port5(struct ds
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mutex_lock(&priv->reg_mutex);
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- val = mt7530_read(priv, MT7530_MHWTRAP);
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+ val = mt7530_read(priv, MT753X_MTRAP);
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- val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
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- val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
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+ val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
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+ val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
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switch (priv->p5_mode) {
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/* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
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case MUX_PHY_P0:
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- val |= MHWTRAP_PHY0_SEL;
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+ val |= MT7530_P5_PHY0_SEL;
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fallthrough;
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/* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
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case MUX_PHY_P4:
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- val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
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+ val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
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/* Setup the MAC by default for the cpu port */
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mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
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@@ -898,13 +899,13 @@ static void mt7530_setup_port5(struct ds
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/* GMAC5: P5 -> SoC MAC or external PHY */
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default:
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- val &= ~MHWTRAP_P5_DIS;
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+ val &= ~MT7530_P5_DIS;
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break;
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}
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/* Setup RGMII settings */
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if (phy_interface_mode_is_rgmii(interface)) {
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- val |= MHWTRAP_P5_RGMII_MODE;
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+ val |= MT7530_P5_RGMII_MODE;
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/* P5 RGMII RX Clock Control: delay setting for 1000M */
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mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
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@@ -924,7 +925,7 @@ static void mt7530_setup_port5(struct ds
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P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
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}
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- mt7530_write(priv, MT7530_MHWTRAP, val);
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+ mt7530_write(priv, MT753X_MTRAP, val);
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dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
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mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
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@@ -2365,7 +2366,7 @@ mt7530_setup(struct dsa_switch *ds)
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}
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/* Waiting for MT7530 got to stable */
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- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
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+ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
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ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
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20, 1000000);
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if (ret < 0) {
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@@ -2380,7 +2381,7 @@ mt7530_setup(struct dsa_switch *ds)
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return -ENODEV;
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}
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- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) {
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+ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) {
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dev_err(priv->dev,
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"MT7530 with a 20MHz XTAL is not supported!\n");
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return -EINVAL;
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@@ -2401,12 +2402,12 @@ mt7530_setup(struct dsa_switch *ds)
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RD_TAP_MASK, RD_TAP(16));
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/* Enable port 6 */
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- val = mt7530_read(priv, MT7530_MHWTRAP);
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- val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
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- val |= MHWTRAP_MANUAL;
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- mt7530_write(priv, MT7530_MHWTRAP, val);
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+ val = mt7530_read(priv, MT753X_MTRAP);
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+ val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
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+ val |= MT7530_CHG_TRAP;
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+ mt7530_write(priv, MT753X_MTRAP, val);
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- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
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+ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
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mt7530_pll_setup(priv);
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mt753x_trap_frames(priv);
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@@ -2586,7 +2587,7 @@ mt7531_setup(struct dsa_switch *ds)
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}
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/* Waiting for MT7530 got to stable */
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- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
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+ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
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ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
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20, 1000000);
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if (ret < 0) {
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--- a/drivers/net/dsa/mt7530.h
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+++ b/drivers/net/dsa/mt7530.h
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@@ -495,32 +495,30 @@ enum mt7531_clk_skew {
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MT7531_CLK_SKEW_REVERSE = 3,
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};
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-/* Register for hw trap status */
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-#define MT7530_HWTRAP 0x7800
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-#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
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-#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
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-#define HWTRAP_XTAL_40MHZ (BIT(10))
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-#define HWTRAP_XTAL_20MHZ (BIT(9))
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+/* Register for trap status */
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+#define MT753X_TRAP 0x7800
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+#define MT7530_XTAL_MASK (BIT(10) | BIT(9))
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+#define MT7530_XTAL_25MHZ (BIT(10) | BIT(9))
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+#define MT7530_XTAL_40MHZ BIT(10)
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+#define MT7530_XTAL_20MHZ BIT(9)
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+#define MT7531_XTAL25 BIT(7)
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-#define MT7531_HWTRAP 0x7800
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-#define HWTRAP_XTAL_FSEL_MASK BIT(7)
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-#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
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-#define HWTRAP_XTAL_FSEL_40MHZ 0
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-/* Unique fields of (M)HWSTRAP for MT7531 */
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-#define XTAL_FSEL_S 7
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-#define XTAL_FSEL_M BIT(7)
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-#define PHY_EN BIT(6)
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-#define CHG_STRAP BIT(8)
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+/* Register for trap modification */
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+#define MT753X_MTRAP 0x7804
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+#define MT7530_P5_PHY0_SEL BIT(20)
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+#define MT7530_CHG_TRAP BIT(16)
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+#define MT7530_P5_MAC_SEL BIT(13)
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+#define MT7530_P6_DIS BIT(8)
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+#define MT7530_P5_RGMII_MODE BIT(7)
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+#define MT7530_P5_DIS BIT(6)
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+#define MT7530_PHY_INDIRECT_ACCESS BIT(5)
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+#define MT7531_CHG_STRAP BIT(8)
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+#define MT7531_PHY_EN BIT(6)
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-/* Register for hw trap modification */
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-#define MT7530_MHWTRAP 0x7804
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-#define MHWTRAP_PHY0_SEL BIT(20)
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-#define MHWTRAP_MANUAL BIT(16)
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-#define MHWTRAP_P5_MAC_SEL BIT(13)
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-#define MHWTRAP_P6_DIS BIT(8)
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-#define MHWTRAP_P5_RGMII_MODE BIT(7)
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-#define MHWTRAP_P5_DIS BIT(6)
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-#define MHWTRAP_PHY_ACCESS BIT(5)
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+enum mt7531_xtal_fsel {
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+ MT7531_XTAL_FSEL_25MHZ,
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+ MT7531_XTAL_FSEL_40MHZ,
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+};
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/* Register for TOP signal control */
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#define MT7530_TOP_SIG_CTRL 0x7808
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