mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-11-25 06:26:15 +00:00
2e0b000e0e
Remove patches that were upstreamed, and backport features from later kernels. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
65 lines
2.5 KiB
Diff
65 lines
2.5 KiB
Diff
From c6fd43b8420f3864ad1cd64d818d9b9abc2cb711 Mon Sep 17 00:00:00 2001
|
|
From: Inochi Amaoto <inochiama@outlook.com>
|
|
Date: Mon, 28 Aug 2023 12:30:22 +0800
|
|
Subject: [PATCH 01/14] riscv: dts: allwinner: d1: Add PMU event node
|
|
|
|
D1 has several pmu events supported by opensbi.
|
|
These events can be used by perf for profiling.
|
|
|
|
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
|
|
Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
|
|
Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
|
|
Acked-by: Conor Dooley <conor.dooley@microchip.com>
|
|
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
|
|
Reviewed-by: Guo Ren <guoren@kernel.org>
|
|
---
|
|
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++
|
|
1 file changed, 39 insertions(+)
|
|
|
|
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
|
|
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
|
|
@@ -72,4 +72,43 @@
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
+
|
|
+ pmu {
|
|
+ compatible = "riscv,pmu";
|
|
+ riscv,event-to-mhpmcounters =
|
|
+ <0x00003 0x00003 0x00000008>,
|
|
+ <0x00004 0x00004 0x00000010>,
|
|
+ <0x00005 0x00005 0x00000200>,
|
|
+ <0x00006 0x00006 0x00000100>,
|
|
+ <0x10000 0x10000 0x00004000>,
|
|
+ <0x10001 0x10001 0x00008000>,
|
|
+ <0x10002 0x10002 0x00010000>,
|
|
+ <0x10003 0x10003 0x00020000>,
|
|
+ <0x10019 0x10019 0x00000040>,
|
|
+ <0x10021 0x10021 0x00000020>;
|
|
+ riscv,event-to-mhpmevent =
|
|
+ <0x00003 0x00000000 0x00000001>,
|
|
+ <0x00004 0x00000000 0x00000002>,
|
|
+ <0x00005 0x00000000 0x00000007>,
|
|
+ <0x00006 0x00000000 0x00000006>,
|
|
+ <0x10000 0x00000000 0x0000000c>,
|
|
+ <0x10001 0x00000000 0x0000000d>,
|
|
+ <0x10002 0x00000000 0x0000000e>,
|
|
+ <0x10003 0x00000000 0x0000000f>,
|
|
+ <0x10019 0x00000000 0x00000004>,
|
|
+ <0x10021 0x00000000 0x00000003>;
|
|
+ riscv,raw-event-to-mhpmcounters =
|
|
+ <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
|
|
+ <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
|
|
+ <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
|
|
+ <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
|
|
+ <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
|
|
+ <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
|
|
+ <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
|
|
+ <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
|
|
+ <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
|
|
+ <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
|
|
+ <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
|
|
+ <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
|
|
+ };
|
|
};
|