mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-11-25 14:36:14 +00:00
b98955c623
late_initcall_sync() is no longer needed so standard module functions can be used on all bmips PCI/PCIe drivers. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
404 lines
11 KiB
C
404 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* BCM6318 PCIe Controller Driver
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*
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* Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
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* Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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*/
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/reset.h>
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#include <linux/types.h>
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#include <linux/version.h>
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#include <linux/vmalloc.h>
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#include "../pci.h"
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#define PCIE_BUS_BRIDGE 0
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#define PCIE_BUS_DEVICE 1
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#define PCIE_SPECIFIC_REG 0x188
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#define SPECIFIC_ENDIAN_MODE_BAR1_SHIFT 0
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#define SPECIFIC_ENDIAN_MODE_BAR1_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
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#define SPECIFIC_ENDIAN_MODE_BAR2_SHIFT 2
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#define SPECIFIC_ENDIAN_MODE_BAR2_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
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#define SPECIFIC_ENDIAN_MODE_BAR3_SHIFT 4
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#define SPECIFIC_ENDIAN_MODE_BAR3_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
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#define SPECIFIC_ENDIAN_MODE_WORD_ALIGN 0
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#define SPECIFIC_ENDIAN_MODE_HALFWORD_ALIGN 1
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#define SPECIFIC_ENDIAN_MODE_BYTE_ALIGN 2
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#define PCIE_CONFIG2_REG 0x408
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#define CONFIG2_BAR1_SIZE_EN 1
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#define CONFIG2_BAR1_SIZE_MASK 0xf
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#define PCIE_IDVAL3_REG 0x43c
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#define IDVAL3_CLASS_CODE_MASK 0xffffff
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#define IDVAL3_SUBCLASS_SHIFT 8
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#define IDVAL3_CLASS_SHIFT 16
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#define PCIE_DLSTATUS_REG 0x1048
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#define DLSTATUS_PHYLINKUP (1 << 13)
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#define PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG 0x400c
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#define C2P_MEM_WIN_ENDIAN_MODE_MASK 0x3
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#define C2P_MEM_WIN_ENDIAN_NO_SWAP 0
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#define C2P_MEM_WIN_ENDIAN_HALF_WORD_SWAP 1
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#define C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP 2
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#define C2P_MEM_WIN_BASE_ADDR_SHIFT 20
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#define C2P_MEM_WIN_BASE_ADDR_MASK (0xfff << C2P_MEM_WIN_BASE_ADDR_SHIFT)
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#define PCIE_RC_BAR1_CONFIG_LO_REG 0x402c
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#define RC_BAR_CFG_LO_SIZE_256MB 0xd
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#define RC_BAR_CFG_LO_MATCH_ADDR_SHIFT 20
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#define RC_BAR_CFG_LO_MATCH_ADDR_MASK (0xfff << RC_BAR_CFG_LO_MATCH_ADDR_SHIFT)
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#define PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG 0x4070
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#define C2P_BASELIMIT_LIMIT_SHIFT 20
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#define C2P_BASELIMIT_LIMIT_MASK (0xfff << C2P_BASELIMIT_LIMIT_SHIFT)
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#define C2P_BASELIMIT_BASE_SHIFT 4
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#define C2P_BASELIMIT_BASE_MASK (0xfff << C2P_BASELIMIT_BASE_SHIFT)
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#define PCIE_UBUS_BAR1_CFG_REMAP_REG 0x4088
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#define BAR1_CFG_REMAP_OFFSET_SHIFT 20
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#define BAR1_CFG_REMAP_OFFSET_MASK (0xfff << BAR1_CFG_REMAP_OFFSET_SHIFT)
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#define BAR1_CFG_REMAP_ACCESS_EN 1
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#define PCIE_HARD_DEBUG_REG 0x4204
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#define HARD_DEBUG_SERDES_IDDQ (1 << 23)
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#define PCIE_CPU_INT1_MASK_CLEAR_REG 0x830c
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#define CPU_INT_PCIE_ERR_ATTN_CPU (1 << 0)
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#define CPU_INT_PCIE_INTA (1 << 1)
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#define CPU_INT_PCIE_INTB (1 << 2)
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#define CPU_INT_PCIE_INTC (1 << 3)
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#define CPU_INT_PCIE_INTD (1 << 4)
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#define CPU_INT_PCIE_INTR (1 << 5)
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#define CPU_INT_PCIE_NMI (1 << 6)
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#define CPU_INT_PCIE_UBUS (1 << 7)
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#define CPU_INT_IPI (1 << 8)
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#define PCIE_EXT_CFG_INDEX_REG 0x8400
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#define EXT_CFG_FUNC_NUM_SHIFT 12
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#define EXT_CFG_FUNC_NUM_MASK (0x7 << EXT_CFG_FUNC_NUM_SHIFT)
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#define EXT_CFG_DEV_NUM_SHIFT 15
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#define EXT_CFG_DEV_NUM_MASK (0xf << EXT_CFG_DEV_NUM_SHIFT)
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#define EXT_CFG_BUS_NUM_SHIFT 20
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#define EXT_CFG_BUS_NUM_MASK (0xff << EXT_CFG_BUS_NUM_SHIFT)
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#define PCIE_DEVICE_OFFSET 0x9000
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struct bcm6318_pcie {
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void __iomem *base;
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int irq;
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struct clk *clk;
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struct clk *clk25;
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struct clk *clk_ubus;
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struct reset_control *reset;
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struct reset_control *reset_ext;
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struct reset_control *reset_core;
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struct reset_control *reset_hard;
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};
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static struct bcm6318_pcie bcm6318_pcie;
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extern int bmips_pci_irq;
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/*
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* swizzle 32bits data to return only the needed part
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*/
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static int postprocess_read(u32 data, int where, unsigned int size)
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{
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u32 ret = 0;
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switch (size) {
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case 1:
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ret = (data >> ((where & 3) << 3)) & 0xff;
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break;
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case 2:
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ret = (data >> ((where & 3) << 3)) & 0xffff;
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break;
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case 4:
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ret = data;
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break;
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}
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return ret;
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}
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static int preprocess_write(u32 orig_data, u32 val, int where,
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unsigned int size)
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{
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u32 ret = 0;
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switch (size) {
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case 1:
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ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 2:
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ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 4:
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ret = val;
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break;
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}
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return ret;
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}
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static int bcm6318_pcie_can_access(struct pci_bus *bus, int devfn)
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{
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struct bcm6318_pcie *priv = &bcm6318_pcie;
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switch (bus->number) {
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case PCIE_BUS_BRIDGE:
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return PCI_SLOT(devfn) == 0;
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case PCIE_BUS_DEVICE:
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if (PCI_SLOT(devfn) == 0)
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return __raw_readl(priv->base + PCIE_DLSTATUS_REG)
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& DLSTATUS_PHYLINKUP;
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fallthrough;
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default:
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return false;
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}
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}
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static int bcm6318_pcie_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct bcm6318_pcie *priv = &bcm6318_pcie;
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u32 data;
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u32 reg = where & ~3;
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if (!bcm6318_pcie_can_access(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (bus->number == PCIE_BUS_DEVICE)
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reg += PCIE_DEVICE_OFFSET;
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data = __raw_readl(priv->base + reg);
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*val = postprocess_read(data, where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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static int bcm6318_pcie_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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struct bcm6318_pcie *priv = &bcm6318_pcie;
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u32 data;
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u32 reg = where & ~3;
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if (!bcm6318_pcie_can_access(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (bus->number == PCIE_BUS_DEVICE)
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reg += PCIE_DEVICE_OFFSET;
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data = __raw_readl(priv->base + reg);
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data = preprocess_write(data, val, where, size);
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__raw_writel(data, priv->base + reg);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops bcm6318_pcie_ops = {
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.read = bcm6318_pcie_read,
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.write = bcm6318_pcie_write,
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};
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static struct resource bcm6318_pcie_io_resource;
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static struct resource bcm6318_pcie_mem_resource;
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static struct resource bcm6318_pcie_busn_resource;
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static struct pci_controller bcm6318_pcie_controller = {
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.pci_ops = &bcm6318_pcie_ops,
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.io_resource = &bcm6318_pcie_io_resource,
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.mem_resource = &bcm6318_pcie_mem_resource,
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};
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static void bcm6318_pcie_reset(struct bcm6318_pcie *priv)
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{
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u32 val;
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reset_control_deassert(priv->reset_hard);
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reset_control_assert(priv->reset);
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reset_control_assert(priv->reset_core);
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reset_control_assert(priv->reset_ext);
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mdelay(10);
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reset_control_deassert(priv->reset_ext);
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mdelay(10);
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reset_control_deassert(priv->reset);
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mdelay(10);
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val = __raw_readl(priv->base + PCIE_HARD_DEBUG_REG);
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val &= ~HARD_DEBUG_SERDES_IDDQ;
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__raw_writel(val, priv->base + PCIE_HARD_DEBUG_REG);
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mdelay(10);
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reset_control_deassert(priv->reset_core);
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mdelay(200);
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}
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static void bcm6318_pcie_setup(struct bcm6318_pcie *priv)
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{
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u32 val;
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__raw_writel(CPU_INT_PCIE_INTA | CPU_INT_PCIE_INTB |
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CPU_INT_PCIE_INTC | CPU_INT_PCIE_INTD,
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priv->base + PCIE_CPU_INT1_MASK_CLEAR_REG);
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val = bcm6318_pcie_mem_resource.end & C2P_BASELIMIT_LIMIT_MASK;
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val |= (bcm6318_pcie_mem_resource.start >> C2P_BASELIMIT_LIMIT_SHIFT)
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<< C2P_BASELIMIT_BASE_SHIFT;
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__raw_writel(val, priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG);
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/* setup class code as bridge */
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val = __raw_readl(priv->base + PCIE_IDVAL3_REG);
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val &= ~IDVAL3_CLASS_CODE_MASK;
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val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
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__raw_writel(val, priv->base + PCIE_IDVAL3_REG);
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/* disable bar1 size */
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val = __raw_readl(priv->base + PCIE_CONFIG2_REG);
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val &= ~CONFIG2_BAR1_SIZE_MASK;
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__raw_writel(val, priv->base + PCIE_CONFIG2_REG);
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/* set bar0 to little endian */
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val = __raw_readl(priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
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val |= bcm6318_pcie_mem_resource.start & C2P_MEM_WIN_BASE_ADDR_MASK;
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val |= C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP;
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__raw_writel(val, priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
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__raw_writel(SPECIFIC_ENDIAN_MODE_BYTE_ALIGN,
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priv->base + PCIE_SPECIFIC_REG);
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__raw_writel(RC_BAR_CFG_LO_SIZE_256MB,
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priv->base + PCIE_RC_BAR1_CONFIG_LO_REG);
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__raw_writel(BAR1_CFG_REMAP_ACCESS_EN,
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priv->base + PCIE_UBUS_BAR1_CFG_REMAP_REG);
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__raw_writel(PCIE_BUS_DEVICE << EXT_CFG_BUS_NUM_SHIFT,
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priv->base + PCIE_EXT_CFG_INDEX_REG);
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}
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static int bcm6318_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct bcm6318_pcie *priv = &bcm6318_pcie;
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struct resource *res;
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int ret;
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LIST_HEAD(resources);
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of_pci_check_probe_only();
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->irq = platform_get_irq(pdev, 0);
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if (!priv->irq)
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return -ENODEV;
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bmips_pci_irq = priv->irq;
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priv->reset = devm_reset_control_get(dev, "pcie");
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if (IS_ERR(priv->reset))
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return PTR_ERR(priv->reset);
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priv->reset_ext = devm_reset_control_get(dev, "pcie-ext");
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if (IS_ERR(priv->reset_ext))
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return PTR_ERR(priv->reset_ext);
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priv->reset_core = devm_reset_control_get(dev, "pcie-core");
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if (IS_ERR(priv->reset_core))
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return PTR_ERR(priv->reset_core);
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priv->reset_hard = devm_reset_control_get(dev, "pcie-hard");
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if (IS_ERR(priv->reset_hard))
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return PTR_ERR(priv->reset_hard);
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priv->clk = devm_clk_get(dev, "pcie");
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if (IS_ERR(priv->clk))
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return PTR_ERR(priv->clk);
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priv->clk25 = devm_clk_get(dev, "pcie25");
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if (IS_ERR(priv->clk25))
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return PTR_ERR(priv->clk25);
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priv->clk_ubus = devm_clk_get(dev, "pcie-ubus");
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if (IS_ERR(priv->clk_ubus))
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return PTR_ERR(priv->clk_ubus);
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ret = clk_prepare_enable(priv->clk);
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if (ret) {
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dev_err(dev, "could not enable clock\n");
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return ret;
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}
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ret = clk_prepare_enable(priv->clk25);
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if (ret) {
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dev_err(dev, "could not enable clock\n");
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return ret;
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}
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ret = clk_prepare_enable(priv->clk_ubus);
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if (ret) {
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dev_err(dev, "could not enable clock\n");
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return ret;
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}
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pci_load_of_ranges(&bcm6318_pcie_controller, np);
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if (!bcm6318_pcie_mem_resource.start)
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return -EINVAL;
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of_pci_parse_bus_range(np, &bcm6318_pcie_busn_resource);
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pci_add_resource(&resources, &bcm6318_pcie_busn_resource);
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bcm6318_pcie_reset(priv);
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bcm6318_pcie_setup(priv);
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register_pci_controller(&bcm6318_pcie_controller);
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return 0;
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}
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static const struct of_device_id bcm6318_pcie_of_match[] = {
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{ .compatible = "brcm,bcm6318-pcie", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, bcm6318_pcie_of_match);
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static struct platform_driver bcm6318_pcie_driver = {
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.probe = bcm6318_pcie_probe,
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.driver = {
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.name = "bcm6318-pcie",
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.of_match_table = bcm6318_pcie_of_match,
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},
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};
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module_platform_driver(bcm6318_pcie_driver);
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MODULE_AUTHOR("Álvaro Fernández Rojas <noltari@gmail.com>");
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MODULE_DESCRIPTION("BCM6318 PCIe Controller Driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:bcm6318-pcie");
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