mirror of
https://git.openwrt.org/openwrt/openwrt.git
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538a1d740c
The patches were generated from the RPi repo with the following command: git format-patch v6.6.58..rpi-6.6.y Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
110 lines
3.6 KiB
Diff
110 lines
3.6 KiB
Diff
From 2b5de12af9bb390239d5f3385c49e0c34f335de8 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Fri, 27 Sep 2024 10:59:02 +0100
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Subject: [PATCH 1289/1350] dts: align PCI BAR allocation on bcm2711 and
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bcm2712 to start at 2GB
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Fold the Pi 5 mmio-hi compatibility option into the base DTB, and
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shuffle the single MMIO window on bcm2711 to match.
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Certain devices cannot handle low addresses, e.g. by failing to
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enumerate or failing to route the traffic appropriately.
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Link: https://github.com/raspberrypi/linux/issues/6134
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Link: https://github.com/raspberrypi/linux/issues/6278
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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.../arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi | 6 +++---
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arch/arm/boot/dts/overlays/README | 2 --
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.../overlays/pciex1-compat-pi5-overlay.dts | 20 -------------------
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arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 10 ++++++----
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4 files changed, 9 insertions(+), 29 deletions(-)
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--- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi
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+++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi
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@@ -123,7 +123,7 @@
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ranges = <0x0 0x7c000000 0x0 0xfc000000 0x0 0x03800000>,
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<0x0 0x40000000 0x0 0xff800000 0x0 0x00800000>,
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- <0x6 0x00000000 0x6 0x00000000 0x0 0x40000000>,
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+ <0x6 0x00000000 0x6 0x00000000 0x0 0x80000000>,
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<0x0 0x00000000 0x0 0x00000000 0x0 0xfc000000>;
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dma-ranges = <0x4 0x7c000000 0x0 0xfc000000 0x0 0x03800000>,
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<0x0 0x00000000 0x0 0x00000000 0x4 0x00000000>;
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@@ -167,8 +167,8 @@
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&pcie0 {
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reg = <0x0 0x7d500000 0x0 0x9310>;
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- ranges = <0x02000000 0x0 0xc0000000 0x6 0x00000000
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- 0x0 0x40000000>;
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+ ranges = <0x02000000 0x0 0x80000000 0x6 0x00000000
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+ 0x0 0x80000000>;
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};
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&genet {
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--- a/arch/arm/boot/dts/overlays/README
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+++ b/arch/arm/boot/dts/overlays/README
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@@ -3617,8 +3617,6 @@ Params: l1ss Enable A
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the MSI-MIP peripheral. Use if a) more than 8
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interrupt vectors are required or b) the EP
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requires DMA and MSI addresses to be 32bit.
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- mmio-hi Move the start of outbound 32bit addresses to
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- 2GB and expand 64bit outbound space to 14GB.
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[ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ]
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--- a/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts
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+++ b/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts
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@@ -32,29 +32,9 @@
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};
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};
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- /*
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- * Shift the start of the 32bit outbound window to 2GB,
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- * so there are no BARs starting at 0x0. Expand the 64bit
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- * outbound window to use the spare 2GB.
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- */
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- fragment@3 {
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- target = <&pciex1>;
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- __dormant__ {
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- #address-cells = <3>;
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- #size-cells = <2>;
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- ranges = <0x02000000 0x00 0x80000000
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- 0x1b 0x80000000
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- 0x00 0x7ffffffc>,
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- <0x43000000 0x04 0x00000000
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- 0x18 0x00000000
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- 0x03 0x80000000>;
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- };
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- };
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-
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__overrides__ {
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l1ss = <0>, "+0";
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no-l0s = <0>, "+1";
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no-mip = <0>, "+2";
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- mmio-hi = <0>, "+3";
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};
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};
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--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
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@@ -1052,12 +1052,14 @@
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msi-controller;
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msi-parent = <&mip1>;
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- ranges = <0x02000000 0x00 0x00000000
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- 0x1b 0x00000000
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- 0x00 0xfffffffc>,
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+ // 2GB, 32-bit, non-prefetchable at PCIe 00_80000000
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+ ranges = <0x02000000 0x00 0x80000000
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+ 0x1b 0x80000000
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+ 0x00 0x80000000>,
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+ // 14GB, 64-bit, prefetchable at PCIe 04_00000000
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<0x43000000 0x04 0x00000000
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0x18 0x00000000
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- 0x03 0x00000000>;
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+ 0x03 0x80000000>;
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dma-ranges = <0x03000000 0x10 0x00000000
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0x00 0x00000000
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