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8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
60 lines
1.7 KiB
Diff
60 lines
1.7 KiB
Diff
From 7f7a5d80c4eb0207713ef938737f56fdebcd1cb3 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Wed, 8 Jun 2022 17:23:47 +0100
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Subject: [PATCH 1062/1085] drm: vc4: dsi: Clocks should be running before
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reset
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The initialisation sequence differs slightly from the documentation
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in that the clocks are meant to be running before resets and
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similar.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_dsi.c | 28 ++++++++++++++--------------
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1 file changed, 14 insertions(+), 14 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_dsi.c
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+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
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@@ -926,6 +926,20 @@ static void vc4_dsi_bridge_pre_enable(st
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"Failed to set phy clock to %ld: %d\n", phy_clock, ret);
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}
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+ ret = clk_prepare_enable(dsi->escape_clock);
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+ if (ret) {
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+ DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
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+ return;
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+ }
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+
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+ ret = clk_prepare_enable(dsi->pll_phy_clock);
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+ if (ret) {
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+ DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
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+ return;
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+ }
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+
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+ hs_clock = clk_get_rate(dsi->pll_phy_clock);
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+
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/* Reset the DSI and all its fifos. */
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DSI_PORT_WRITE(CTRL,
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DSI_CTRL_SOFT_RESET_CFG |
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@@ -984,20 +998,6 @@ static void vc4_dsi_bridge_pre_enable(st
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mdelay(1);
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}
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- ret = clk_prepare_enable(dsi->escape_clock);
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- if (ret) {
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- DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
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- return;
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- }
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-
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- ret = clk_prepare_enable(dsi->pll_phy_clock);
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- if (ret) {
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- DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
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- return;
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- }
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-
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- hs_clock = clk_get_rate(dsi->pll_phy_clock);
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-
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/* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
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* not the pixel clock rate. DSIxP take from the APHY's byte,
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* DDR2, or DDR4 clock (we use byte) and feed into the PV at
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