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8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
108 lines
4.1 KiB
Diff
108 lines
4.1 KiB
Diff
From 85cc26d5496f073fc7e5dc33f8c9fd5c7aea93c6 Mon Sep 17 00:00:00 2001
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From: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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Date: Mon, 22 Apr 2024 13:06:21 +0100
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Subject: [PATCH 1050/1085] DRM: rp1: rp1-dsi: Fix escape clock divider and
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timeouts.
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Escape clock divider was fixed at 5, which is correct at 800Mbps/lane
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but increasingly out of spec for higher rates. Compute it correctly.
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High speed timeout was fixed at 5*512 == 2560 byte-clocks per lane.
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Compute it conservatively to be 8/7 times the line period (assuming
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there will be a transition to LP some time during each scanline?)
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keeping the old value as a lower bound. Increase LPRX TO to 1024,
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and BTA TO to 0xb00 (same value as in bridge/synopsys/dw-mipi-dsi).
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(No change to LP_CMD_TIM. To do: compute this correctly.)
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Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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---
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drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c | 39 ++++++++++++++---------
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1 file changed, 24 insertions(+), 15 deletions(-)
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--- a/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c
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+++ b/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c
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@@ -1336,10 +1336,17 @@ static u32 get_colorcode(enum mipi_dsi_p
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return 0x005;
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}
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+/* Maximum frequency for LP escape clock (20MHz), and some magic numbers */
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+#define RP1DSI_ESC_CLK_KHZ 20000
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+#define RP1DSI_TO_CLK_DIV 5
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+#define RP1DSI_HSTX_TO_MIN 0x200
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+#define RP1DSI_LPRX_TO_VAL 0x400
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+#define RP1DSI_BTA_TO_VAL 0xd00
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+
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void rp1dsi_dsi_setup(struct rp1_dsi *dsi, struct drm_display_mode const *mode)
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{
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u32 timeout, mask, vid_mode_cfg;
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- u32 freq_khz;
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+ int lane_kbps;
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unsigned int bpp = mipi_dsi_pixel_format_to_bpp(dsi->display_format);
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DSI_WRITE(DSI_PHY_IF_CFG, dsi->lanes - 1);
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@@ -1349,28 +1356,33 @@ void rp1dsi_dsi_setup(struct rp1_dsi *ds
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/* a conservative guess (LP escape is slow!) */
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DSI_WRITE(DSI_DPI_LP_CMD_TIM, 0x00100000);
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- /* Drop to LP where possible */
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+ /* Drop to LP where possible; use LP Escape for all commands */
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vid_mode_cfg = 0xbf00;
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if (!(dsi->display_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
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vid_mode_cfg |= 0x01;
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if (dsi->display_flags & MIPI_DSI_MODE_VIDEO_BURST)
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vid_mode_cfg |= 0x02;
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DSI_WRITE(DSI_VID_MODE_CFG, vid_mode_cfg);
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-
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- /* Use LP Escape Data signalling for all commands */
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DSI_WRITE(DSI_CMD_MODE_CFG, 0x10F7F00);
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+
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/* Select Command Mode */
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DSI_WRITE(DSI_MODE_CFG, 1);
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- /* XXX magic number */
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- DSI_WRITE(DSI_TO_CNT_CFG, 0x02000200);
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- /* XXX magic number */
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- DSI_WRITE(DSI_BTA_TO_CNT, 0x800);
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+ /* Set timeouts and clock dividers */
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+ DSI_WRITE(DSI_TO_CNT_CFG,
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+ (max((bpp * mode->htotal) / (7 * RP1DSI_TO_CLK_DIV * dsi->lanes),
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+ RP1DSI_HSTX_TO_MIN) << 16) |
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+ RP1DSI_LPRX_TO_VAL);
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+ DSI_WRITE(DSI_BTA_TO_CNT, RP1DSI_BTA_TO_VAL);
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+ lane_kbps = (bpp * mode->clock) / dsi->lanes;
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+ DSI_WRITE(DSI_CLKMGR_CFG,
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+ (RP1DSI_TO_CLK_DIV << 8) |
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+ max(2, lane_kbps / (8 * RP1DSI_ESC_CLK_KHZ) + 1));
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+
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+ /* Configure video timings */
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DSI_WRITE(DSI_VID_PKT_SIZE, mode->hdisplay);
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DSI_WRITE(DSI_VID_NUM_CHUNKS, 0);
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DSI_WRITE(DSI_VID_NULL_SIZE, 0);
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-
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- /* Note, unlike Argon firmware, here we DON'T consider sync to be concurrent with porch */
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DSI_WRITE(DSI_VID_HSA_TIME,
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(bpp * (mode->hsync_end - mode->hsync_start)) / (8 * dsi->lanes));
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DSI_WRITE(DSI_VID_HBP_TIME,
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@@ -1381,9 +1393,8 @@ void rp1dsi_dsi_setup(struct rp1_dsi *ds
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DSI_WRITE(DSI_VID_VFP_LINES, (mode->vsync_start - mode->vdisplay));
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DSI_WRITE(DSI_VID_VACTIVE_LINES, mode->vdisplay);
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- freq_khz = (bpp * mode->clock) / dsi->lanes;
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-
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- dphy_init_khz(dsi, rp1dsi_refclk_freq(dsi) / 1000, freq_khz);
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+ /* Init PHY */
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+ dphy_init_khz(dsi, rp1dsi_refclk_freq(dsi) / 1000, lane_kbps);
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DSI_WRITE(DSI_PHY_TMR_LPCLK_CFG,
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(hsfreq_table[dsi->hsfreq_index].clk_lp2hs << DSI_PHY_TMR_LP2HS_LSB) |
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@@ -1392,8 +1403,6 @@ void rp1dsi_dsi_setup(struct rp1_dsi *ds
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(hsfreq_table[dsi->hsfreq_index].data_lp2hs << DSI_PHY_TMR_LP2HS_LSB) |
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(hsfreq_table[dsi->hsfreq_index].data_hs2lp << DSI_PHY_TMR_HS2LP_LSB));
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- DSI_WRITE(DSI_CLKMGR_CFG, 0x00000505);
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-
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/* Wait for PLL lock */
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for (timeout = (1 << 14); timeout != 0; --timeout) {
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usleep_range(10, 50);
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