mirror of
https://git.openwrt.org/openwrt/openwrt.git
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8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
154 lines
4.7 KiB
Diff
154 lines
4.7 KiB
Diff
From bbb70265fd52ea75bd59c6d23632418dd905bad1 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Fri, 22 Mar 2024 14:41:07 +0000
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Subject: [PATCH 0987/1085] ARM: dts: bcm2712: Add the missing L1/L2/L3 cache
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information
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This provides the missing cache information for bcm2712
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lscpu now reports:
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Caches (sum of all):
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L1d: 256 KiB (4 instances)
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L1i: 256 KiB (4 instances)
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L2: 2 MiB (4 instances)
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L3: 2 MiB (1 instance)
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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arch/arm/boot/dts/broadcom/bcm2712.dtsi | 89 +++++++++++++++++++++++--
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1 file changed, 84 insertions(+), 5 deletions(-)
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--- a/arch/arm/boot/dts/broadcom/bcm2712.dtsi
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+++ b/arch/arm/boot/dts/broadcom/bcm2712.dtsi
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@@ -750,12 +750,22 @@
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#size-cells = <0>;
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enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
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+ /* Source for d/i cache-line-size, cache-sets, cache-size
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+ * https://developer.arm.com/documentation/100798/0401
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+ * /L1-memory-system/About-the-L1-memory-system?lang=en
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+ */
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x000>;
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enable-method = "psci";
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- next-level-cache = <&l2_cache>;
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+ d-cache-size = <0x10000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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+ i-cache-size = <0x10000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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+ next-level-cache = <&l2_cache_l0>;
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};
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cpu1: cpu@1 {
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@@ -763,7 +773,13 @@
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compatible = "arm,cortex-a76";
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reg = <0x100>;
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enable-method = "psci";
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- next-level-cache = <&l2_cache>;
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+ d-cache-size = <0x10000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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+ i-cache-size = <0x10000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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+ next-level-cache = <&l2_cache_l1>;
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};
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cpu2: cpu@2 {
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@@ -771,7 +787,13 @@
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compatible = "arm,cortex-a76";
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reg = <0x200>;
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enable-method = "psci";
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- next-level-cache = <&l2_cache>;
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+ d-cache-size = <0x10000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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+ i-cache-size = <0x10000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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+ next-level-cache = <&l2_cache_l2>;
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};
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cpu3: cpu@3 {
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@@ -779,16 +801,73 @@
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compatible = "arm,cortex-a76";
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reg = <0x300>;
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enable-method = "psci";
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- next-level-cache = <&l2_cache>;
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+ d-cache-size = <0x10000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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+ i-cache-size = <0x10000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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+ next-level-cache = <&l2_cache_l3>;
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+ };
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+
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+ /* Source for cache-line-size and cache-sets:
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+ * https://developer.arm.com/documentation/100798/0401
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+ * /L2-memory-system/About-the-L2-memory-system?lang=en
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+ * and for cache-size:
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+ * https://www.raspberrypi.com/documentation/computers
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+ * /processors.html#bcm2712
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+ */
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+ l2_cache_l0: l2-cache-l0 {
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+ compatible = "cache";
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+ cache-size = <0x80000>;
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+ cache-line-size = <128>;
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+ cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
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+ cache-level = <2>;
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+ cache-unified;
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+ next-level-cache = <&l3_cache>;
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+ };
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+
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+ l2_cache_l1: l2-cache-l1 {
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+ compatible = "cache";
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+ cache-size = <0x80000>;
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+ cache-line-size = <128>;
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+ cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
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+ cache-level = <2>;
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+ cache-unified;
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+ next-level-cache = <&l3_cache>;
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+ };
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+
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+ l2_cache_l2: l2-cache-l2 {
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+ compatible = "cache";
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+ cache-size = <0x80000>;
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+ cache-line-size = <128>;
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+ cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
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+ cache-level = <2>;
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+ cache-unified;
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+ next-level-cache = <&l3_cache>;
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};
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- l2_cache: l2-cache {
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+ l2_cache_l3: l2-cache-l3 {
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compatible = "cache";
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+ cache-size = <0x80000>;
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+ cache-line-size = <128>;
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+ cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
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+ cache-level = <2>;
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+ cache-unified;
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next-level-cache = <&l3_cache>;
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};
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+ /* Source for cache-line-size and cache-sets:
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+ * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
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+ * Source for cache-size:
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+ * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
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+ */
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l3_cache: l3-cache {
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compatible = "cache";
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+ cache-size = <0x200000>;
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+ cache-line-size = <64>;
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+ cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
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+ cache-level = <3>;
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};
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};
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