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01d8e41c16
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.51 Removed upstreamed: generic/backport-6.6/200-regmap-maple-work-around-false-positive-warning.patch generic/backport-6.6/822-v6.11-0012-nvmem-Fix-return-type-of-devm_nvmem_device_get-in-ke.patch bcm27xx/patches-6.6/950-1018-drivers-mmc-apply-SD-quirks-earlier-during-probe.patch Manually rebased: bcm27xx/patches-6.6/950-0993-drivers-mmc-cqhci-clear-CQHCI_CTL-if-halt-fails.patch ramips/patches-6.6/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch[4] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.51&id=e42ea96d6d36a16526cb82b8aa2e5422814c3250 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.51&id=3d1baf322a3a69b38b6b2d511cfe0d611d1b5462 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.51&id=115a755bb38db5a1175be44e6a9a93a0a8233885 4. Adapted the changes from Hauke Mehrtens' modification in PR#16366 to 5.15.167 Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/16370 Signed-off-by: Robert Marko <robimarko@gmail.com>
248 lines
7.5 KiB
Diff
248 lines
7.5 KiB
Diff
From d8d078e82e4aff1f1a9427ce7a0841c283e0dc53 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Fri, 15 Mar 2024 13:06:13 +0000
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Subject: [PATCH 0980/1085] drivers: mmc: add SD support for Command Queueing
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Application class A2 cards require CQ to be enabled to realise their
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stated performance figures. Add support to enable/disable card CQ via
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the Performance Enhancement extension register, and cater for the slight
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differences in command set versus eMMC.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/mmc/core/block.c | 26 +++++++++++++++++-----
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drivers/mmc/core/core.c | 6 ++++-
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drivers/mmc/core/sd.c | 46 ++++++++++++++++++++++++++++++++++-----
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drivers/mmc/core/sd_ops.c | 37 +++++++++++++++++++++++++++++++
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drivers/mmc/core/sd_ops.h | 2 ++
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include/linux/mmc/sd.h | 12 ++++++++++
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6 files changed, 116 insertions(+), 13 deletions(-)
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--- a/drivers/mmc/core/block.c
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+++ b/drivers/mmc/core/block.c
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@@ -887,7 +887,10 @@ static int mmc_blk_part_switch_pre(struc
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if ((part_type & mask) == rpmb) {
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if (card->ext_csd.cmdq_en) {
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- ret = mmc_cmdq_disable(card);
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+ if (mmc_card_sd(card))
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+ ret = mmc_sd_cmdq_disable(card);
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+ else
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+ ret = mmc_cmdq_disable(card);
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if (ret)
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return ret;
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}
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@@ -906,8 +909,12 @@ static int mmc_blk_part_switch_post(stru
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if ((part_type & mask) == rpmb) {
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mmc_retune_unpause(card->host);
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- if (card->reenable_cmdq && !card->ext_csd.cmdq_en)
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- ret = mmc_cmdq_enable(card);
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+ if (card->reenable_cmdq && !card->ext_csd.cmdq_en) {
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+ if (mmc_card_sd(card))
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+ ret = mmc_sd_cmdq_enable(card);
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+ else
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+ ret = mmc_cmdq_enable(card);
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+ }
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}
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return ret;
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@@ -1103,7 +1110,10 @@ static void mmc_blk_issue_drv_op(struct
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switch (mq_rq->drv_op) {
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case MMC_DRV_OP_IOCTL:
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if (card->ext_csd.cmdq_en) {
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- ret = mmc_cmdq_disable(card);
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+ if (mmc_card_sd(card))
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+ ret = mmc_sd_cmdq_disable(card);
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+ else
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+ ret = mmc_cmdq_disable(card);
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if (ret)
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break;
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}
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@@ -1121,8 +1131,12 @@ static void mmc_blk_issue_drv_op(struct
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/* Always switch back to main area after RPMB access */
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if (rpmb_ioctl)
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mmc_blk_part_switch(card, 0);
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- else if (card->reenable_cmdq && !card->ext_csd.cmdq_en)
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- mmc_cmdq_enable(card);
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+ else if (card->reenable_cmdq && !card->ext_csd.cmdq_en) {
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+ if (mmc_card_sd(card))
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+ mmc_sd_cmdq_enable(card);
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+ else
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+ mmc_cmdq_enable(card);
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+ }
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break;
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case MMC_DRV_OP_BOOT_WP:
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ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP,
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--- a/drivers/mmc/core/core.c
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+++ b/drivers/mmc/core/core.c
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@@ -556,7 +556,11 @@ int mmc_cqe_recovery(struct mmc_host *ho
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mmc_poll_for_busy(host->card, MMC_CQE_RECOVERY_TIMEOUT, true, MMC_BUSY_IO);
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memset(&cmd, 0, sizeof(cmd));
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- cmd.opcode = MMC_CMDQ_TASK_MGMT;
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+ if (mmc_card_sd(host->card))
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+ cmd.opcode = SD_CMDQ_TASK_MGMT;
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+ else
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+ cmd.opcode = MMC_CMDQ_TASK_MGMT;
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+
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cmd.arg = 1; /* Discard entire queue */
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cmd.flags = MMC_RSP_R1B | MMC_CMD_AC;
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cmd.flags &= ~MMC_RSP_CRC; /* Ignore CRC */
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--- a/drivers/mmc/core/sd.c
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+++ b/drivers/mmc/core/sd.c
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@@ -1016,8 +1016,8 @@ static bool mmc_sd_card_using_v18(struct
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(SD_MODE_UHS_SDR50 | SD_MODE_UHS_SDR104 | SD_MODE_UHS_DDR50);
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}
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-static int sd_write_ext_reg(struct mmc_card *card, u8 fno, u8 page, u16 offset,
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- u8 reg_data)
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+int sd_write_ext_reg(struct mmc_card *card, u8 fno, u8 page, u16 offset,
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+ u8 reg_data)
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{
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struct mmc_host *host = card->host;
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struct mmc_request mrq = {};
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@@ -1175,8 +1175,14 @@ static int sd_parse_ext_reg_perf(struct
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card->ext_perf.feature_support |= SD_EXT_PERF_CACHE;
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/* Command queue support indicated via queue depth bits (0 to 4). */
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- if (reg_buf[6] & 0x1f)
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+ if (reg_buf[6] & 0x1f) {
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card->ext_perf.feature_support |= SD_EXT_PERF_CMD_QUEUE;
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+ card->ext_csd.cmdq_depth = reg_buf[6] & 0x1f;
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+ card->ext_csd.cmdq_support = true;
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+ pr_debug("%s: Command Queue supported depth %u\n",
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+ mmc_hostname(card->host),
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+ card->ext_csd.cmdq_depth);
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+ }
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card->ext_perf.fno = fno;
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card->ext_perf.page = page;
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@@ -1563,13 +1569,41 @@ cont:
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goto free_card;
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}
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+ /* Enable command queueing if supported */
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+ if (card->ext_csd.cmdq_support && host->caps2 & MMC_CAP2_CQE) {
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+ /*
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+ * Right now the MMC block layer uses DCMDs to issue
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+ * cache-flush commands specific to eMMC devices.
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+ * Turning off DCMD support avoids generating Illegal Command
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+ * errors on SD, and flushing is instead done synchronously
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+ * by mmc_blk_issue_flush().
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+ */
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+ host->caps2 &= ~MMC_CAP2_CQE_DCMD;
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+ err = mmc_sd_cmdq_enable(card);
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+ if (err && err != -EBADMSG)
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+ goto free_card;
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+ if (err) {
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+ pr_warn("%s: Enabling CMDQ failed\n",
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+ mmc_hostname(card->host));
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+ card->ext_csd.cmdq_support = false;
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+ card->ext_csd.cmdq_depth = 0;
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+ }
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+ }
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+ card->reenable_cmdq = card->ext_csd.cmdq_en;
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+
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if (host->cqe_ops && !host->cqe_enabled) {
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err = host->cqe_ops->cqe_enable(host, card);
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if (!err) {
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host->cqe_enabled = true;
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- host->hsq_enabled = true;
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- pr_info("%s: Host Software Queue enabled\n",
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- mmc_hostname(host));
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+
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+ if (card->ext_csd.cmdq_en) {
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+ pr_info("%s: Command Queue Engine enabled\n",
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+ mmc_hostname(host));
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+ } else {
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+ host->hsq_enabled = true;
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+ pr_info("%s: Host Software Queue enabled\n",
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+ mmc_hostname(host));
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+ }
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}
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}
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--- a/drivers/mmc/core/sd_ops.c
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+++ b/drivers/mmc/core/sd_ops.c
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@@ -365,3 +365,40 @@ int mmc_app_sd_status(struct mmc_card *c
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return 0;
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}
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+
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+int sd_write_ext_reg(struct mmc_card *card, u8 fno, u8 page, u16 offset,
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+ u8 reg_data);
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+
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+static int mmc_sd_cmdq_switch(struct mmc_card *card, bool enable)
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+{
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+ int err;
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+ u8 reg = 0;
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+ /*
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+ * SD offers two command queueing modes - sequential (in-order) and
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+ * voluntary (out-of-order). Apps Class A2 performance is only
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+ * guaranteed for voluntary CQ (bit 1 = 0), so use that in preference
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+ * to sequential.
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+ */
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+ if (enable)
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+ reg = BIT(0);
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+
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+ /* Performance enhancement register byte 262 controls command queueing */
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+ err = sd_write_ext_reg(card, card->ext_perf.fno, card->ext_perf.page,
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+ card->ext_perf.offset + 262, reg);
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+ if (!err)
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+ card->ext_csd.cmdq_en = enable;
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+
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+ return err;
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+}
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+
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+int mmc_sd_cmdq_enable(struct mmc_card *card)
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+{
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+ return mmc_sd_cmdq_switch(card, true);
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+}
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+EXPORT_SYMBOL_GPL(mmc_sd_cmdq_enable);
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+
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+int mmc_sd_cmdq_disable(struct mmc_card *card)
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+{
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+ return mmc_sd_cmdq_switch(card, false);
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+}
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+EXPORT_SYMBOL_GPL(mmc_sd_cmdq_disable);
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--- a/drivers/mmc/core/sd_ops.h
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+++ b/drivers/mmc/core/sd_ops.h
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@@ -21,6 +21,8 @@ int mmc_send_relative_addr(struct mmc_ho
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int mmc_app_send_scr(struct mmc_card *card);
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int mmc_app_sd_status(struct mmc_card *card, void *ssr);
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int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card);
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+int mmc_sd_cmdq_enable(struct mmc_card *card);
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+int mmc_sd_cmdq_disable(struct mmc_card *card);
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#endif
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--- a/include/linux/mmc/sd.h
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+++ b/include/linux/mmc/sd.h
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@@ -29,6 +29,9 @@
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#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
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#define SD_APP_SEND_SCR 51 /* adtc R1 */
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+ /* class 1 */
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+#define SD_CMDQ_TASK_MGMT 43 /* ac See below R1b */
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+
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/* class 11 */
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#define SD_READ_EXTR_SINGLE 48 /* adtc [31:0] R1 */
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#define SD_WRITE_EXTR_SINGLE 49 /* adtc [31:0] R1 */
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@@ -61,6 +64,15 @@
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*/
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/*
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+ * SD_CMDQ_TASK_MGMT argument format:
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+ *
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+ * [31:21] Reserved (0)
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+ * [20:16] Task ID
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+ * [15:4] Reserved (0)
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+ * [3:0] Operation - 0x1 = abort all tasks, 0x2 = abort Task ID
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+ */
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+
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+/*
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* SCR field definitions
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*/
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