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openwrt/target/linux/bcm27xx/patches-6.6/950-0961-ARM-dts-Set-all-RPi-PWM-clocks-to-50MHz.patch
Álvaro Fernández Rojas 8c405cdccc bcm27xx: add 6.6 kernel patches
The patches were generated from the RPi repo with the following command:
git format-patch v6.6.34..rpi-6.1.y

Some patches needed rebasing and, as usual, the applied and reverted, wireless
drivers, Github workflows, READMEs and defconfigs patches were removed.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2024-06-18 18:52:49 +02:00

115 lines
3.7 KiB
Diff

From 80c57b7437fb6f55b879f921f3118a2deb0c15a8 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.com>
Date: Tue, 12 Mar 2024 10:16:58 +0000
Subject: [PATCH 0961/1085] ARM: dts: Set all RPi PWM clocks to 50MHz
With the RP1 PWM configured to use the 50MHz oscillator clock source,
requesting a 100MHz clock will fail. Set the RP1 PWM clock rate to
50MHz, do the same to other Pi PWM blocks, and remove the default
clock override in the PWM overlays. However, an explicit
"clock=..." parameter is still supported.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
---
arch/arm/boot/dts/broadcom/bcm2711.dtsi | 2 +-
arch/arm/boot/dts/broadcom/bcm2712.dtsi | 4 ++--
arch/arm/boot/dts/broadcom/bcm283x.dtsi | 2 +-
arch/arm/boot/dts/broadcom/rp1.dtsi | 4 ++--
arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts | 1 -
arch/arm/boot/dts/overlays/pwm-overlay.dts | 1 -
arch/arm/boot/dts/overlays/pwm1-overlay.dts | 1 -
7 files changed, 6 insertions(+), 9 deletions(-)
--- a/arch/arm/boot/dts/broadcom/bcm2711.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi
@@ -277,7 +277,7 @@
reg = <0x7e20c800 0x28>;
clocks = <&clocks BCM2835_CLOCK_PWM>;
assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
- assigned-clock-rates = <10000000>;
+ assigned-clock-rates = <50000000>;
#pwm-cells = <3>;
status = "disabled";
};
--- a/arch/arm/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm2712.dtsi
@@ -345,7 +345,7 @@
pwm0: pwm@7d00c000 {
compatible = "brcm,bcm2835-pwm";
reg = <0x7d00c000 0x28>;
- assigned-clock-rates = <10000000>;
+ assigned-clock-rates = <50000000>;
#pwm-cells = <3>;
status = "disabled";
};
@@ -353,7 +353,7 @@
pwm1: pwm@7d00c800 {
compatible = "brcm,bcm2835-pwm";
reg = <0x7d00c800 0x28>;
- assigned-clock-rates = <10000000>;
+ assigned-clock-rates = <50000000>;
#pwm-cells = <3>;
status = "disabled";
};
--- a/arch/arm/boot/dts/broadcom/bcm283x.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm283x.dtsi
@@ -415,7 +415,7 @@
reg = <0x7e20c000 0x28>;
clocks = <&clocks BCM2835_CLOCK_PWM>;
assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
- assigned-clock-rates = <10000000>;
+ assigned-clock-rates = <50000000>;
#pwm-cells = <3>;
status = "disabled";
};
--- a/arch/arm/boot/dts/broadcom/rp1.dtsi
+++ b/arch/arm/boot/dts/broadcom/rp1.dtsi
@@ -376,7 +376,7 @@
#pwm-cells = <3>;
clocks = <&rp1_clocks RP1_CLK_PWM0>;
assigned-clocks = <&rp1_clocks RP1_CLK_PWM0>;
- assigned-clock-rates = <6144000>;
+ assigned-clock-rates = <50000000>;
status = "disabled";
};
@@ -386,7 +386,7 @@
#pwm-cells = <3>;
clocks = <&rp1_clocks RP1_CLK_PWM1>;
assigned-clocks = <&rp1_clocks RP1_CLK_PWM1>;
- assigned-clock-rates = <6144000>;
+ assigned-clock-rates = <50000000>;
status = "disabled";
};
--- a/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts
+++ b/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts
@@ -34,7 +34,6 @@ N.B.:
frag1: __overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
- assigned-clock-rates = <100000000>;
status = "okay";
};
};
--- a/arch/arm/boot/dts/overlays/pwm-overlay.dts
+++ b/arch/arm/boot/dts/overlays/pwm-overlay.dts
@@ -32,7 +32,6 @@ N.B.:
frag1: __overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
- assigned-clock-rates = <100000000>;
status = "okay";
};
};
--- a/arch/arm/boot/dts/overlays/pwm1-overlay.dts
+++ b/arch/arm/boot/dts/overlays/pwm1-overlay.dts
@@ -42,7 +42,6 @@
target = <&pwm1>;
pwm: __overlay__ {
status = "okay";
- assigned-clock-rates = <100000000>;
pinctrl-names = "default";
pinctrl-0 = <&pins>;
};