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8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
257 lines
8.8 KiB
Diff
257 lines
8.8 KiB
Diff
From 610e5b7cc8a05a7895471e17276379bc6d582b89 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Fri, 1 Apr 2022 18:56:54 +0100
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Subject: [PATCH 0459/1085] media: i2c: imx258: Support faster pixel rate on
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binned modes
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With the binned modes, there is little point in faithfully
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reproducing the horizontal line length of 5352 pixels on the CSI2
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bus, and the FIFO between the pixel array and MIPI serialiser
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allows us to remove that dependency.
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Allow the pixel array to run with the normal settings, with the MIPI
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serialiser at half the rate. This requires some additional
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information for the link frequency to pixel rate function that
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needs to be added to the configuration tables.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/media/i2c/imx258.c | 109 ++++++++++++++++++++++++-------------
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1 file changed, 71 insertions(+), 38 deletions(-)
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--- a/drivers/media/i2c/imx258.c
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+++ b/drivers/media/i2c/imx258.c
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@@ -103,6 +103,11 @@ struct imx258_reg_list {
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const struct imx258_reg *regs;
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};
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+struct imx258_link_cfg {
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+ unsigned int lf_to_pix_rate_factor;
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+ struct imx258_reg_list reg_list;
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+};
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+
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#define IMX258_LANE_CONFIGS 2
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#define IMX258_2_LANE_MODE 0
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#define IMX258_4_LANE_MODE 1
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@@ -112,8 +117,8 @@ struct imx258_link_freq_config {
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u64 link_frequency;
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u32 pixels_per_line;
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- /* PLL registers for this link frequency */
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- struct imx258_reg_list reg_list[IMX258_LANE_CONFIGS];
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+ /* Configuration for this link frequency / num lanes selection */
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+ struct imx258_link_cfg link_cfg[IMX258_LANE_CONFIGS];
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};
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/* Mode : resolution and related config&values */
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@@ -272,7 +277,7 @@ static const struct imx258_reg mipi_640m
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static const struct imx258_reg mipi_642mbps_24mhz_2l[] = {
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{ 0x0136, 0x18 },
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{ 0x0137, 0x00 },
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- { 0x0301, 0x0A },
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+ { 0x0301, 0x05 },
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{ 0x0303, 0x02 },
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{ 0x0305, 0x04 },
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{ 0x0306, 0x00 },
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@@ -673,14 +678,22 @@ enum {
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};
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/*
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- * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
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- * data rate => double data rate;
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- * number of lanes => (configurable 2 or 4);
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- * bits per pixel => 10
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+ * Pixel rate does not necessarily relate to link frequency on this sensor as
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+ * there is a FIFO between the pixel array pipeline and the MIPI serializer.
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+ * The recommendation from Sony is that the pixel array is always run with a
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+ * line length of 5352 pixels, which means that there is a large amount of
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+ * blanking time for the 1048x780 mode. There is no need to replicate this
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+ * blanking on the CSI2 bus, and the configuration of register 0x0301 allows the
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+ * divider to be altered.
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+ *
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+ * The actual factor between link frequency and pixel rate is in the
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+ * imx258_link_cfg, so use this to convert between the two.
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+ * bits per pixel being 10, and D-PHY being DDR is assumed by this function, so
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+ * the value is only the combination of number of lanes and pixel clock divider.
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*/
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-static u64 link_freq_to_pixel_rate(u64 f, unsigned int nlanes)
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+static u64 link_freq_to_pixel_rate(u64 f, const struct imx258_link_cfg *link_cfg)
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{
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- f *= 2 * nlanes;
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+ f *= 2 * link_cfg->lf_to_pix_rate_factor;
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do_div(f, 10);
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return f;
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@@ -705,31 +718,33 @@ static const s64 link_freq_menu_items_24
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IMX258_LINK_FREQ_321MHZ,
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};
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+#define REGS(_list) { .num_of_regs = ARRAY_SIZE(_list), .regs = _list, }
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+
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/* Link frequency configs */
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static const struct imx258_link_freq_config link_freq_configs_19_2[] = {
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[IMX258_LINK_FREQ_1267MBPS] = {
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.pixels_per_line = IMX258_PPL_DEFAULT,
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- .reg_list = {
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+ .link_cfg = {
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[IMX258_2_LANE_MODE] = {
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- .num_of_regs = ARRAY_SIZE(mipi_1267mbps_19_2mhz_2l),
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- .regs = mipi_1267mbps_19_2mhz_2l,
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+ .lf_to_pix_rate_factor = 2 * 2,
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+ .reg_list = REGS(mipi_1267mbps_19_2mhz_2l),
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},
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[IMX258_4_LANE_MODE] = {
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- .num_of_regs = ARRAY_SIZE(mipi_1267mbps_19_2mhz_4l),
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- .regs = mipi_1267mbps_19_2mhz_4l,
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+ .lf_to_pix_rate_factor = 4,
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+ .reg_list = REGS(mipi_1267mbps_19_2mhz_4l),
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},
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}
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},
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[IMX258_LINK_FREQ_640MBPS] = {
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.pixels_per_line = IMX258_PPL_DEFAULT,
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- .reg_list = {
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+ .link_cfg = {
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[IMX258_2_LANE_MODE] = {
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- .num_of_regs = ARRAY_SIZE(mipi_640mbps_19_2mhz_2l),
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- .regs = mipi_640mbps_19_2mhz_2l,
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+ .lf_to_pix_rate_factor = 2,
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+ .reg_list = REGS(mipi_640mbps_19_2mhz_2l),
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},
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[IMX258_4_LANE_MODE] = {
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- .num_of_regs = ARRAY_SIZE(mipi_640mbps_19_2mhz_4l),
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- .regs = mipi_640mbps_19_2mhz_4l,
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+ .lf_to_pix_rate_factor = 4,
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+ .reg_list = REGS(mipi_640mbps_19_2mhz_4l),
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},
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}
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},
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@@ -738,27 +753,27 @@ static const struct imx258_link_freq_con
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static const struct imx258_link_freq_config link_freq_configs_24[] = {
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[IMX258_LINK_FREQ_1267MBPS] = {
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.pixels_per_line = IMX258_PPL_DEFAULT,
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- .reg_list = {
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+ .link_cfg = {
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[IMX258_2_LANE_MODE] = {
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- .num_of_regs = ARRAY_SIZE(mipi_1272mbps_24mhz_2l),
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- .regs = mipi_1272mbps_24mhz_2l,
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+ .lf_to_pix_rate_factor = 2,
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+ .reg_list = REGS(mipi_1272mbps_24mhz_2l),
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},
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[IMX258_4_LANE_MODE] = {
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- .num_of_regs = ARRAY_SIZE(mipi_1272mbps_24mhz_4l),
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- .regs = mipi_1272mbps_24mhz_4l,
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+ .lf_to_pix_rate_factor = 4,
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+ .reg_list = REGS(mipi_1272mbps_24mhz_4l),
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},
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}
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},
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[IMX258_LINK_FREQ_640MBPS] = {
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.pixels_per_line = IMX258_PPL_DEFAULT,
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- .reg_list = {
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+ .link_cfg = {
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[IMX258_2_LANE_MODE] = {
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- .num_of_regs = ARRAY_SIZE(mipi_642mbps_24mhz_2l),
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- .regs = mipi_642mbps_24mhz_2l,
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+ .lf_to_pix_rate_factor = 2 * 2,
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+ .reg_list = REGS(mipi_642mbps_24mhz_2l),
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},
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[IMX258_4_LANE_MODE] = {
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- .num_of_regs = ARRAY_SIZE(mipi_642mbps_24mhz_4l),
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- .regs = mipi_642mbps_24mhz_4l,
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+ .lf_to_pix_rate_factor = 4,
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+ .reg_list = REGS(mipi_642mbps_24mhz_4l),
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},
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}
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},
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@@ -838,7 +853,7 @@ struct imx258 {
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const struct imx258_link_freq_config *link_freq_configs;
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const s64 *link_freq_menu_items;
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- unsigned int nlanes;
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+ unsigned int lane_mode_idx;
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unsigned int csi2_flags;
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/*
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@@ -1171,8 +1186,10 @@ static int imx258_set_pad_format(struct
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struct v4l2_subdev_format *fmt)
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{
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struct imx258 *imx258 = to_imx258(sd);
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- const struct imx258_mode *mode;
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+ const struct imx258_link_freq_config *link_freq_cfgs;
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+ const struct imx258_link_cfg *link_cfg;
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struct v4l2_mbus_framefmt *framefmt;
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+ const struct imx258_mode *mode;
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s32 vblank_def;
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s32 vblank_min;
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s64 h_blank;
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@@ -1196,7 +1213,11 @@ static int imx258_set_pad_format(struct
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__v4l2_ctrl_s_ctrl(imx258->link_freq, mode->link_freq_index);
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link_freq = imx258->link_freq_menu_items[mode->link_freq_index];
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- pixel_rate = link_freq_to_pixel_rate(link_freq, imx258->nlanes);
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+ link_freq_cfgs =
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+ &imx258->link_freq_configs[mode->link_freq_index];
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+
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+ link_cfg = &link_freq_cfgs->link_cfg[imx258->lane_mode_idx];
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+ pixel_rate = link_freq_to_pixel_rate(link_freq, link_cfg);
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__v4l2_ctrl_modify_range(imx258->pixel_rate, pixel_rate,
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pixel_rate, 1, pixel_rate);
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/* Update limits and set FPS to default */
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@@ -1293,7 +1314,8 @@ static int imx258_start_streaming(struct
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/* Setup PLL */
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link_freq_index = imx258->cur_mode->link_freq_index;
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link_freq_cfg = &imx258->link_freq_configs[link_freq_index];
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- reg_list = &link_freq_cfg->reg_list[imx258->nlanes == 2 ? 0 : 1];
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+
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+ reg_list = &link_freq_cfg->link_cfg[imx258->lane_mode_idx].reg_list;
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ret = imx258_write_regs(imx258, reg_list->regs, reg_list->num_of_regs);
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if (ret) {
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dev_err(&client->dev, "%s failed to set plls\n", __func__);
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@@ -1512,9 +1534,11 @@ static const struct v4l2_subdev_internal
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static int imx258_init_controls(struct imx258 *imx258)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
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+ const struct imx258_link_freq_config *link_freq_cfgs;
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struct v4l2_fwnode_device_properties props;
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- struct v4l2_ctrl_handler *ctrl_hdlr;
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struct v4l2_ctrl *vflip, *hflip;
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+ struct v4l2_ctrl_handler *ctrl_hdlr;
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+ const struct imx258_link_cfg *link_cfg;
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s64 vblank_def;
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s64 vblank_min;
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s64 pixel_rate;
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@@ -1548,8 +1572,11 @@ static int imx258_init_controls(struct i
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if (vflip)
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vflip->flags |= V4L2_CTRL_FLAG_READ_ONLY;
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+ link_freq_cfgs = &imx258->link_freq_configs[0];
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+ link_cfg = link_freq_cfgs[imx258->lane_mode_idx].link_cfg;
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pixel_rate = link_freq_to_pixel_rate(imx258->link_freq_menu_items[0],
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- imx258->nlanes);
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+ link_cfg);
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+
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/* By default, PIXEL_RATE is read only */
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imx258->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops,
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V4L2_CID_PIXEL_RATE,
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@@ -1710,10 +1737,16 @@ static int imx258_probe(struct i2c_clien
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}
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/* Get number of data lanes */
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- imx258->nlanes = ep.bus.mipi_csi2.num_data_lanes;
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- if (imx258->nlanes != 2 && imx258->nlanes != 4) {
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+ switch (ep.bus.mipi_csi2.num_data_lanes) {
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+ case 2:
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+ imx258->lane_mode_idx = IMX258_2_LANE_MODE;
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+ break;
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+ case 4:
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+ imx258->lane_mode_idx = IMX258_4_LANE_MODE;
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+ break;
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+ default:
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dev_err(&client->dev, "Invalid data lanes: %u\n",
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- imx258->nlanes);
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+ ep.bus.mipi_csi2.num_data_lanes);
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ret = -EINVAL;
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goto error_endpoint_poweron;
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}
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