mirror of
https://git.openwrt.org/openwrt/openwrt.git
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8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
402 lines
14 KiB
Diff
402 lines
14 KiB
Diff
From bd8bb0ed9c5908f84502ee76a152370291727eef Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Thu, 16 Dec 2021 14:54:54 +0100
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Subject: [PATCH 0030/1085] drm/vc4: hvs: Defer dlist slots deallocation
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During normal operations, the cursor position update is done through an
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asynchronous plane update, which on the vc4 driver basically just
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modifies the right dlist word to move the plane to the new coordinates.
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However, when we have the overscan margins setup, we fall back to a
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regular commit when we are next to the edges. And since that commit
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happens to be on a cursor plane, it's considered a legacy cursor update
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by KMS.
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The main difference it makes is that it won't wait for its completion
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(ie, next vblank) before returning. This means if we have multiple
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commits happening in rapid succession, we can have several of them
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happening before the next vblank.
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In parallel, our dlist allocation is tied to a CRTC state, and each time
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we do a commit we end up with a new CRTC state, with the previous one
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being freed. This means that we free our previous dlist entry (but don't
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clear it though) every time a new one is being committed.
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Now, if we were to have two commits happening before the next vblank, we
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could end up freeing reusing the same dlist entries before the next
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vblank.
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Indeed, we would start from an initial state taking, for example, the
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dlist entries 10 to 20, then start a commit taking the entries 20 to 30
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and setting the dlist pointer to 20, and freeing the dlist entries 10 to
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20. However, since we haven't reach vblank yet, the HVS is still using
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the entries 10 to 20.
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If we were to make a new commit now, chances are the allocator are going
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to give the 10 to 20 entries back, and we would change their content to
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match the new state. If vblank hasn't happened yet, we just corrupted
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the active dlist entries.
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A first attempt to solve this was made by creating an intermediate dlist
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buffer to store the current (ie, as of the last commit) dlist content,
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that we would update each time the HVS is done with a frame. However, if
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the interrupt handler missed the vblank window, we would end up copying
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our intermediate dlist to the hardware one during the composition,
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essentially creating the same issue.
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Since making sure that our interrupt handler runs within a fixed,
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constrained, time window would require to make Linux a real-time kernel,
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this seems a bit out of scope.
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Instead, we can work around our original issue by keeping the dlist
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slots allocation longer. That way, we won't reuse a dlist slot while
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it's still in flight. In order to achieve this, instead of freeing the
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dlist slot when its associated CRTC state is destroyed, we'll queue it
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in a list.
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A naive implementation would free the buffers in that queue when we get
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our end of frame interrupt. However, there's still a race since, just
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like in the shadow dlist case, we don't control when the handler for
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that interrupt is going to run. Thus, we can end up with a commit adding
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an old dlist allocation to our queue during the window between our
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actual interrupt and when our handler will run. And since that buffer is
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still being used for the composition of the current frame, we can't free
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it right away, exposing us to the original bug.
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Fortunately for us, the hardware provides a frame counter that is
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increased each time the first line of a frame is being generated.
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Associating the frame counter the image is supposed to go away to the
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allocation, and then only deallocate buffers that have a counter below
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or equal to the one we see when the deallocation code should prevent the
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above race from occuring.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 10 +-
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drivers/gpu/drm/vc4/vc4_drv.h | 15 ++-
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drivers/gpu/drm/vc4/vc4_hvs.c | 184 ++++++++++++++++++++++++++++++---
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3 files changed, 186 insertions(+), 23 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -1097,14 +1097,8 @@ void vc4_crtc_destroy_state(struct drm_c
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struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
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- if (drm_mm_node_allocated(&vc4_state->mm)) {
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- unsigned long flags;
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-
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- spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
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- drm_mm_remove_node(&vc4_state->mm);
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- spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
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-
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- }
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+ vc4_hvs_mark_dlist_entry_stale(vc4->hvs, vc4_state->mm);
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+ vc4_state->mm = NULL;
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drm_atomic_helper_crtc_destroy_state(crtc, state);
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}
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -332,6 +332,9 @@ struct vc4_hvs {
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struct drm_mm lbm_mm;
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spinlock_t mm_lock;
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+ struct list_head stale_dlist_entries;
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+ struct work_struct free_dlist_work;
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+
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struct drm_mm_node mitchell_netravali_filter;
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struct debugfs_regset32 regset;
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@@ -619,10 +622,16 @@ struct drm_connector *vc4_get_crtc_conne
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struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,
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struct drm_crtc_state *state);
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+struct vc4_hvs_dlist_allocation {
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+ struct list_head node;
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+ struct drm_mm_node mm_node;
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+ unsigned int channel;
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+ u8 target_frame_count;
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+};
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+
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struct vc4_crtc_state {
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struct drm_crtc_state base;
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- /* Dlist area for this CRTC configuration. */
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- struct drm_mm_node mm;
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+ struct vc4_hvs_dlist_allocation *mm;
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bool txp_armed;
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unsigned int assigned_channel;
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@@ -1032,6 +1041,8 @@ struct vc4_hvs *__vc4_hvs_alloc(struct v
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void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int output);
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int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output);
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u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo);
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+void vc4_hvs_mark_dlist_entry_stale(struct vc4_hvs *hvs,
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+ struct vc4_hvs_dlist_allocation *alloc);
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int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);
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void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state);
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void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -412,6 +412,152 @@ static void vc5_hvs_update_gamma_lut(str
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vc5_hvs_lut_load(hvs, vc4_crtc);
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}
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+static void vc4_hvs_irq_enable_eof(const struct vc4_hvs *hvs,
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+ unsigned int channel)
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+{
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+ struct vc4_dev *vc4 = hvs->vc4;
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+ u32 irq_mask = vc4->is_vc5 ?
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+ SCALER5_DISPCTRL_DSPEIEOF(channel) :
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+ SCALER_DISPCTRL_DSPEIEOF(channel);
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+
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+ HVS_WRITE(SCALER_DISPCTRL,
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+ HVS_READ(SCALER_DISPCTRL) | irq_mask);
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+}
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+
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+static void vc4_hvs_irq_clear_eof(const struct vc4_hvs *hvs,
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+ unsigned int channel)
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+{
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+ struct vc4_dev *vc4 = hvs->vc4;
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+ u32 irq_mask = vc4->is_vc5 ?
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+ SCALER5_DISPCTRL_DSPEIEOF(channel) :
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+ SCALER_DISPCTRL_DSPEIEOF(channel);
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+
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+ HVS_WRITE(SCALER_DISPCTRL,
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+ HVS_READ(SCALER_DISPCTRL) & ~irq_mask);
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+}
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+
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+static struct vc4_hvs_dlist_allocation *
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+vc4_hvs_alloc_dlist_entry(struct vc4_hvs *hvs,
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+ unsigned int channel,
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+ size_t dlist_count)
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+{
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+ struct vc4_hvs_dlist_allocation *alloc;
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+ unsigned long flags;
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+ int ret;
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+
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+ if (channel == VC4_HVS_CHANNEL_DISABLED)
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+ return NULL;
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+
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+ alloc = kzalloc(sizeof(*alloc), GFP_KERNEL);
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+ if (!alloc)
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+ return ERR_PTR(-ENOMEM);
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+
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+ spin_lock_irqsave(&hvs->mm_lock, flags);
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+ ret = drm_mm_insert_node(&hvs->dlist_mm, &alloc->mm_node,
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+ dlist_count);
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+ spin_unlock_irqrestore(&hvs->mm_lock, flags);
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+ if (ret)
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+ return ERR_PTR(ret);
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+
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+ alloc->channel = channel;
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+
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+ return alloc;
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+}
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+
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+void vc4_hvs_mark_dlist_entry_stale(struct vc4_hvs *hvs,
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+ struct vc4_hvs_dlist_allocation *alloc)
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+{
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+ unsigned long flags;
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+ u8 frcnt;
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+
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+ if (!alloc)
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+ return;
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+
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+ if (!drm_mm_node_allocated(&alloc->mm_node))
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+ return;
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+
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+ frcnt = vc4_hvs_get_fifo_frame_count(hvs, alloc->channel);
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+ alloc->target_frame_count = (frcnt + 1) & ((1 << 6) - 1);
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+
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+ spin_lock_irqsave(&hvs->mm_lock, flags);
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+
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+ list_add_tail(&alloc->node, &hvs->stale_dlist_entries);
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+
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+ HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_EOF(alloc->channel));
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+ vc4_hvs_irq_enable_eof(hvs, alloc->channel);
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+
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+ spin_unlock_irqrestore(&hvs->mm_lock, flags);
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+}
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+
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+static void vc4_hvs_schedule_dlist_sweep(struct vc4_hvs *hvs,
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+ unsigned int channel)
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+{
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&hvs->mm_lock, flags);
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+
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+ if (!list_empty(&hvs->stale_dlist_entries))
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+ queue_work(system_unbound_wq, &hvs->free_dlist_work);
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+
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+ vc4_hvs_irq_clear_eof(hvs, channel);
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+
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+ spin_unlock_irqrestore(&hvs->mm_lock, flags);
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+}
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+
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+/*
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+ * Frame counts are essentially sequence numbers over 6 bits, and we
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+ * thus can use sequence number arithmetic and follow the RFC1982 to
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+ * implement proper comparison between them.
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+ */
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+static bool vc4_hvs_frcnt_lte(u8 cnt1, u8 cnt2)
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+{
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+ return (s8)((cnt1 << 2) - (cnt2 << 2)) <= 0;
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+}
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+
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+/*
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+ * Some atomic commits (legacy cursor updates, mostly) will not wait for
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+ * the next vblank and will just return once the commit has been pushed
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+ * to the hardware.
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+ *
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+ * On the hardware side, our HVS stores the planes parameters in its
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+ * context RAM, and will use part of the RAM to store data during the
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+ * frame rendering.
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+ *
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+ * This interacts badly if we get multiple commits before the next
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+ * vblank since we could end up overwriting the DLIST entries used by
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+ * previous commits if our dlist allocation reuses that entry. In such a
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+ * case, we would overwrite the data currently being used by the
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+ * hardware, resulting in a corrupted frame.
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+ *
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+ * In order to work around this, we'll queue the dlist entries in a list
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+ * once the associated CRTC state is destroyed. The HVS only allows us
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+ * to know which entry is being active, but not which one are no longer
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+ * being used, so in order to avoid freeing entries that are still used
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+ * by the hardware we add a guesstimate of the frame count where our
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+ * entry will no longer be used, and thus will only free those entries
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+ * when we will have reached that frame count.
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+ */
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+static void vc4_hvs_dlist_free_work(struct work_struct *work)
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+{
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+ struct vc4_hvs *hvs = container_of(work, struct vc4_hvs, free_dlist_work);
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+ struct vc4_hvs_dlist_allocation *cur, *next;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&hvs->mm_lock, flags);
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+ list_for_each_entry_safe(cur, next, &hvs->stale_dlist_entries, node) {
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+ u8 frcnt;
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+
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+ frcnt = vc4_hvs_get_fifo_frame_count(hvs, cur->channel);
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+ if (!vc4_hvs_frcnt_lte(cur->target_frame_count, frcnt))
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+ continue;
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+
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+ list_del(&cur->node);
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+ drm_mm_remove_node(&cur->mm_node);
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+ kfree(cur);
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+ }
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+ spin_unlock_irqrestore(&hvs->mm_lock, flags);
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+}
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+
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u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo)
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{
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struct drm_device *drm = &hvs->vc4->base;
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@@ -643,13 +789,12 @@ int vc4_hvs_atomic_check(struct drm_crtc
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{
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struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
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+ struct vc4_hvs_dlist_allocation *alloc;
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct drm_plane *plane;
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- unsigned long flags;
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const struct drm_plane_state *plane_state;
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u32 dlist_count = 0;
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- int ret;
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/* The pixelvalve can only feed one encoder (and encoders are
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* 1:1 with connectors.)
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@@ -662,12 +807,11 @@ int vc4_hvs_atomic_check(struct drm_crtc
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dlist_count++; /* Account for SCALER_CTL0_END. */
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- spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
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- ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
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- dlist_count);
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- spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
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- if (ret)
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- return ret;
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+ alloc = vc4_hvs_alloc_dlist_entry(vc4->hvs, vc4_state->assigned_channel, dlist_count);
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+ if (IS_ERR(alloc))
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+ return PTR_ERR(alloc);
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+
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+ vc4_state->mm = alloc;
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return vc4_hvs_gamma_check(crtc, state);
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}
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@@ -683,8 +827,9 @@ static void vc4_hvs_install_dlist(struct
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if (!drm_dev_enter(dev, &idx))
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return;
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+ WARN_ON(!vc4_state->mm);
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HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
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- vc4_state->mm.start);
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+ vc4_state->mm->mm_node.start);
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drm_dev_exit(idx);
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}
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@@ -711,8 +856,10 @@ static void vc4_hvs_update_dlist(struct
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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+ WARN_ON(!vc4_state->mm);
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+
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spin_lock_irqsave(&vc4_crtc->irq_lock, flags);
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- vc4_crtc->current_dlist = vc4_state->mm.start;
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+ vc4_crtc->current_dlist = vc4_state->mm->mm_node.start;
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spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags);
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}
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@@ -769,8 +916,7 @@ void vc4_hvs_atomic_flush(struct drm_crt
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struct vc4_plane_state *vc4_plane_state;
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bool debug_dump_regs = false;
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bool enable_bg_fill = false;
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- u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
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- u32 __iomem *dlist_next = dlist_start;
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+ u32 __iomem *dlist_start, *dlist_next;
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unsigned int zpos = 0;
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bool found = false;
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int idx;
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@@ -788,6 +934,9 @@ void vc4_hvs_atomic_flush(struct drm_crt
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vc4_hvs_dump_state(hvs);
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}
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+ dlist_start = vc4->hvs->dlist + vc4_state->mm->mm_node.start;
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+ dlist_next = dlist_start;
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+
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/* Copy all the active planes' dlist contents to the hardware dlist. */
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do {
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found = false;
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@@ -821,7 +970,8 @@ void vc4_hvs_atomic_flush(struct drm_crt
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writel(SCALER_CTL0_END, dlist_next);
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dlist_next++;
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- WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
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+ WARN_ON(!vc4_state->mm);
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+ WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm->mm_node.size);
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if (enable_bg_fill)
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/* This sets a black background color fill, as is the case
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@@ -960,6 +1110,11 @@ static irqreturn_t vc4_hvs_irq_handler(i
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irqret = IRQ_HANDLED;
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}
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+
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+ if (status & SCALER_DISPSTAT_EOF(channel)) {
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+ vc4_hvs_schedule_dlist_sweep(hvs, channel);
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+ irqret = IRQ_HANDLED;
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+ }
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}
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/* Clear every per-channel interrupt flag. */
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@@ -1014,6 +1169,9 @@ struct vc4_hvs *__vc4_hvs_alloc(struct v
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spin_lock_init(&hvs->mm_lock);
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+ INIT_LIST_HEAD(&hvs->stale_dlist_entries);
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+ INIT_WORK(&hvs->free_dlist_work, vc4_hvs_dlist_free_work);
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+
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/* Set up the HVS display list memory manager. We never
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* overwrite the setup from the bootloader (just 128b out of
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* our 16K), since we don't want to scramble the screen when
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