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https://git.openwrt.org/openwrt/openwrt.git
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8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
277 lines
9.3 KiB
Diff
277 lines
9.3 KiB
Diff
From efed9f6403c125e56b9852b81f81632e85feb2eb Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Tue, 27 Apr 2021 14:24:21 +0200
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Subject: [PATCH 0008/1085] drm/vc4: Add support for gamma on BCM2711
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BCM2711 changes from a 256 entry lookup table to a 16 point
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piecewise linear function as the pipeline bitdepth has increased
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to make a LUT unwieldy.
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Implement a simple conversion from a 256 entry LUT that userspace
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is likely to expect to 16 evenly spread points in the PWL. This
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could be improved with curve fitting at a later date.
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Co-developed-by: Juerg Haefliger <juergh@canonical.com>
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Signed-off-by: Juerg Haefliger <juergh@canonical.com>
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 35 ++++++++++---
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drivers/gpu/drm/vc4/vc4_drv.h | 28 +++++++++--
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drivers/gpu/drm/vc4/vc4_hvs.c | 89 ++++++++++++++++++++++++++++++++--
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drivers/gpu/drm/vc4/vc4_regs.h | 22 +++++++++
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4 files changed, 162 insertions(+), 12 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -1340,19 +1340,42 @@ int __vc4_crtc_init(struct drm_device *d
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if (!vc4->is_vc5) {
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drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
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+ } else {
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+ /* This is a lie for hvs5 which uses a 16 point PWL, but it
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+ * allows for something smarter than just 16 linearly spaced
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+ * segments. Conversion is done in vc5_hvs_update_gamma_lut.
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+ */
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+ drm_mode_crtc_set_gamma_size(crtc, 256);
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+ }
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- drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
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+ drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
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+ if (!vc4->is_vc5) {
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/* We support CTM, but only for one CRTC at a time. It's therefore
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* implemented as private driver state in vc4_kms, not here.
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*/
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drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
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- }
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- for (i = 0; i < crtc->gamma_size; i++) {
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- vc4_crtc->lut_r[i] = i;
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- vc4_crtc->lut_g[i] = i;
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- vc4_crtc->lut_b[i] = i;
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+ /* Initialize the VC4 gamma LUTs */
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+ for (i = 0; i < crtc->gamma_size; i++) {
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+ vc4_crtc->lut_r[i] = i;
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+ vc4_crtc->lut_g[i] = i;
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+ vc4_crtc->lut_b[i] = i;
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+ }
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+ } else {
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+ /* Initialize the VC5 gamma PWL entries. Assume 12-bit pipeline,
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+ * evenly spread over full range.
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+ */
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+ for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++) {
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+ vc4_crtc->pwl_r[i] =
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+ VC5_HVS_SET_GAMMA_ENTRY(i << 8, i << 12, 1 << 8);
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+ vc4_crtc->pwl_g[i] =
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+ VC5_HVS_SET_GAMMA_ENTRY(i << 8, i << 12, 1 << 8);
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+ vc4_crtc->pwl_b[i] =
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+ VC5_HVS_SET_GAMMA_ENTRY(i << 8, i << 12, 1 << 8);
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+ vc4_crtc->pwl_a[i] =
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+ VC5_HVS_SET_GAMMA_ENTRY(i << 8, i << 12, 1 << 8);
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+ }
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}
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return 0;
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -22,6 +22,7 @@
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#include <kunit/test-bug.h>
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#include "uapi/drm/vc4_drm.h"
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+#include "vc4_regs.h"
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struct drm_device;
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struct drm_gem_object;
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@@ -494,6 +495,17 @@ struct drm_encoder *vc4_find_encoder_by_
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return NULL;
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}
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+struct vc5_gamma_entry {
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+ u32 x_c_terms;
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+ u32 grad_term;
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+};
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+
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+#define VC5_HVS_SET_GAMMA_ENTRY(x, c, g) (struct vc5_gamma_entry){ \
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+ .x_c_terms = VC4_SET_FIELD((x), SCALER5_DSPGAMMA_OFF_X) | \
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+ VC4_SET_FIELD((c), SCALER5_DSPGAMMA_OFF_C), \
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+ .grad_term = (g) \
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+}
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+
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struct vc4_crtc_data {
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const char *name;
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@@ -538,9 +550,19 @@ struct vc4_crtc {
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/* Timestamp at start of vblank irq - unaffected by lock delays. */
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ktime_t t_vblank;
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- u8 lut_r[256];
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- u8 lut_g[256];
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- u8 lut_b[256];
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+ union {
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+ struct { /* VC4 gamma LUT */
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+ u8 lut_r[256];
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+ u8 lut_g[256];
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+ u8 lut_b[256];
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+ };
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+ struct { /* VC5 gamma PWL entries */
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+ struct vc5_gamma_entry pwl_r[SCALER5_DSPGAMMA_NUM_POINTS];
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+ struct vc5_gamma_entry pwl_g[SCALER5_DSPGAMMA_NUM_POINTS];
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+ struct vc5_gamma_entry pwl_b[SCALER5_DSPGAMMA_NUM_POINTS];
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+ struct vc5_gamma_entry pwl_a[SCALER5_DSPGAMMA_NUM_POINTS];
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+ };
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+ };
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struct drm_pending_vblank_event *event;
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -243,7 +243,8 @@ static void vc4_hvs_lut_load(struct vc4_
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static void vc4_hvs_update_gamma_lut(struct vc4_hvs *hvs,
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struct vc4_crtc *vc4_crtc)
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{
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- struct drm_crtc_state *crtc_state = vc4_crtc->base.state;
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+ struct drm_crtc *crtc = &vc4_crtc->base;
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+ struct drm_crtc_state *crtc_state = crtc->state;
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struct drm_color_lut *lut = crtc_state->gamma_lut->data;
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u32 length = drm_color_lut_size(crtc_state->gamma_lut);
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u32 i;
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@@ -257,6 +258,81 @@ static void vc4_hvs_update_gamma_lut(str
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vc4_hvs_lut_load(hvs, vc4_crtc);
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}
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+static void vc5_hvs_write_gamma_entry(struct vc4_hvs *hvs,
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+ u32 offset,
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+ struct vc5_gamma_entry *gamma)
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+{
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+ HVS_WRITE(offset, gamma->x_c_terms);
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+ HVS_WRITE(offset + 4, gamma->grad_term);
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+}
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+
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+static void vc5_hvs_lut_load(struct vc4_hvs *hvs,
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+ struct vc4_crtc *vc4_crtc)
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+{
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+ struct drm_crtc *crtc = &vc4_crtc->base;
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+ struct drm_crtc_state *crtc_state = crtc->state;
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+ struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
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+ u32 i;
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+ u32 offset = SCALER5_DSPGAMMA_START +
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+ vc4_state->assigned_channel * SCALER5_DSPGAMMA_CHAN_OFFSET;
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+
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+ for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++, offset += 8)
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+ vc5_hvs_write_gamma_entry(hvs, offset, &vc4_crtc->pwl_r[i]);
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+ for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++, offset += 8)
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+ vc5_hvs_write_gamma_entry(hvs, offset, &vc4_crtc->pwl_g[i]);
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+ for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++, offset += 8)
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+ vc5_hvs_write_gamma_entry(hvs, offset, &vc4_crtc->pwl_b[i]);
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+
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+ if (vc4_state->assigned_channel == 2) {
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+ /* Alpha only valid on channel 2 */
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+ for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++, offset += 8)
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+ vc5_hvs_write_gamma_entry(hvs, offset, &vc4_crtc->pwl_a[i]);
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+ }
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+}
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+
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+static void vc5_hvs_update_gamma_lut(struct vc4_hvs *hvs,
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+ struct vc4_crtc *vc4_crtc)
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+{
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+ struct drm_crtc *crtc = &vc4_crtc->base;
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+ struct drm_color_lut *lut = crtc->state->gamma_lut->data;
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+ unsigned int step, i;
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+ u32 start, end;
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+
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+#define VC5_HVS_UPDATE_GAMMA_ENTRY_FROM_LUT(pwl, chan) \
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+ start = drm_color_lut_extract(lut[i * step].chan, 12); \
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+ end = drm_color_lut_extract(lut[(i + 1) * step - 1].chan, 12); \
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+ \
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+ /* Negative gradients not permitted by the hardware, so \
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+ * flatten such points out. \
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+ */ \
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+ if (end < start) \
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+ end = start; \
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+ \
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+ /* Assume 12bit pipeline. \
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+ * X evenly spread over full range (12 bit). \
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+ * C as U12.4 format. \
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+ * Gradient as U4.8 format. \
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+ */ \
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+ vc4_crtc->pwl[i] = \
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+ VC5_HVS_SET_GAMMA_ENTRY(i << 8, start << 4, \
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+ ((end - start) << 4) / (step - 1))
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+
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+ /* HVS5 has a 16 point piecewise linear function for each colour
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+ * channel (including alpha on channel 2) on each display channel.
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+ *
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+ * Currently take a crude subsample of the gamma LUT, but this could
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+ * be improved to implement curve fitting.
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+ */
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+ step = crtc->gamma_size / SCALER5_DSPGAMMA_NUM_POINTS;
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+ for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++) {
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+ VC5_HVS_UPDATE_GAMMA_ENTRY_FROM_LUT(pwl_r, red);
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+ VC5_HVS_UPDATE_GAMMA_ENTRY_FROM_LUT(pwl_g, green);
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+ VC5_HVS_UPDATE_GAMMA_ENTRY_FROM_LUT(pwl_b, blue);
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+ }
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+
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+ vc5_hvs_lut_load(hvs, vc4_crtc);
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+}
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+
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u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo)
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{
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struct drm_device *drm = &hvs->vc4->base;
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@@ -400,7 +476,10 @@ static int vc4_hvs_init_channel(struct v
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/* Reload the LUT, since the SRAMs would have been disabled if
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* all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
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*/
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- vc4_hvs_lut_load(hvs, vc4_crtc);
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+ if (!vc4->is_vc5)
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+ vc4_hvs_lut_load(hvs, vc4_crtc);
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+ else
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+ vc5_hvs_lut_load(hvs, vc4_crtc);
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drm_dev_exit(idx);
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@@ -646,7 +725,11 @@ void vc4_hvs_atomic_flush(struct drm_crt
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u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel));
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if (crtc->state->gamma_lut) {
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- vc4_hvs_update_gamma_lut(hvs, vc4_crtc);
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+ if (!vc4->is_vc5)
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+ vc4_hvs_update_gamma_lut(hvs, vc4_crtc);
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+ else
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+ vc5_hvs_update_gamma_lut(hvs, vc4_crtc);
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+
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dispbkgndx |= SCALER_DISPBKGND_GAMMA;
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} else {
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/* Unsetting DISPBKGND_GAMMA skips the gamma lut step
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -512,6 +512,28 @@
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#define SCALER_DLIST_START 0x00002000
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#define SCALER_DLIST_SIZE 0x00004000
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+/* Gamma PWL for each channel. 16 points for each of 4 colour channels (alpha
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+ * only on channel 2). 8 bytes per entry, offsets first, then gradient:
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+ * Y = GRAD * X + C
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+ *
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+ * Values for X and C are left justified, and vary depending on the width of
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+ * the HVS channel:
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+ * 8-bit pipeline: X uses [31:24], C is U8.8 format, and GRAD is U4.8.
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+ * 12-bit pipeline: X uses [31:20], C is U12.4 format, and GRAD is U4.8.
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+ *
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+ * The 3 HVS channels start at 0x400 offsets (ie chan 1 starts at 0x2400, and
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+ * chan 2 at 0x2800).
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+ */
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+#define SCALER5_DSPGAMMA_NUM_POINTS 16
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+#define SCALER5_DSPGAMMA_START 0x00002000
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+#define SCALER5_DSPGAMMA_CHAN_OFFSET 0x400
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+# define SCALER5_DSPGAMMA_OFF_X_MASK VC4_MASK(31, 20)
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+# define SCALER5_DSPGAMMA_OFF_X_SHIFT 20
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+# define SCALER5_DSPGAMMA_OFF_C_MASK VC4_MASK(15, 0)
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+# define SCALER5_DSPGAMMA_OFF_C_SHIFT 0
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+# define SCALER5_DSPGAMMA_GRAD_MASK VC4_MASK(11, 0)
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+# define SCALER5_DSPGAMMA_GRAD_SHIFT 0
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+
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#define SCALER5_DLIST_START 0x00004000
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# define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
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