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9131cb44ff
Introduce EN7581 SoC support with currently rfb board supported. This is a new 64bit SoC from Airoha that is currently almost fully supported upstream with only the DTS missing. Setting source-only waiting for the full upstream support to be completed. Link: https://github.com/openwrt/openwrt/pull/16730 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
188 lines
6.3 KiB
Diff
188 lines
6.3 KiB
Diff
--- /dev/null
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+++ b/drivers/tty/serial/8250/8250_en7523.c
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@@ -0,0 +1,94 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Airoha EN7523 driver.
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+ *
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+ * Copyright (c) 2022 Genexis Sweden AB
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+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
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+ */
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+#include <linux/clk.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/of_irq.h>
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+#include <linux/of_platform.h>
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+#include <linux/pinctrl/consumer.h>
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+#include <linux/platform_device.h>
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+#include <linux/pm_runtime.h>
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+#include <linux/serial_8250.h>
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+#include <linux/serial_reg.h>
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+#include <linux/console.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/tty.h>
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+#include <linux/tty_flip.h>
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+
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+#include "8250.h"
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+
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+
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+/* The Airoha UART is 16550-compatible except for the baud rate calculation.
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+ *
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+ * crystal_clock = 20 MHz
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+ * xindiv_clock = crystal_clock / clock_div
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+ * (x/y) = XYD, 32 bit register with 16 bits of x and and then 16 bits of y
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+ * clock_div = XINCLK_DIVCNT (default set to 10 (0x4)),
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+ * - 3 bit register [ 1, 2, 4, 8, 10, 12, 16, 20 ]
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+ *
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+ * baud_rate = ((xindiv_clock) * (x/y)) / ([BRDH,BRDL] * 16)
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+ *
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+ * XYD_y seems to need to be larger then XYD_x for things to work.
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+ * Setting [BRDH,BRDL] to [0,1] and XYD_y to 65000 give even values
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+ * for usual baud rates.
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+ *
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+ * Selecting divider needs to fulfill
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+ * 1.8432 MHz <= xindiv_clk <= APB clock / 2
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+ * The clocks are unknown but a divider of value 1 did not work.
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+ *
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+ * Optimally the XYD, BRD and XINCLK_DIVCNT registers could be searched to
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+ * find values that gives the least error for every baud rate. But searching
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+ * the space takes time and in practise only a few rates are of interest.
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+ * With some value combinations not working a tested subset is used giving
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+ * a usable range from 110 to 460800 baud.
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+ */
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+
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+#define CLOCK_DIV_TAB_ELEMS 3
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+#define XYD_Y 65000
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+#define XINDIV_CLOCK 20000000
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+#define UART_BRDL_20M 0x01
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+#define UART_BRDH_20M 0x00
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+
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+static int clock_div_tab[] = { 10, 4, 2};
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+static int clock_div_reg[] = { 4, 2, 1};
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+
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+
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+int en7523_set_uart_baud_rate (struct uart_port *port, unsigned int baud)
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+{
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+ struct uart_8250_port *up = up_to_u8250p(port);
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+ unsigned int xyd_x, nom, denom;
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+ int i;
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+
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+ /* set DLAB to access the baud rate divider registers (BRDH, BRDL) */
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+ serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
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+
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+ /* set baud rate calculation defaults */
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+
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+ /* set BRDIV ([BRDH,BRDL]) to 1 */
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+ serial_port_out(port, UART_BRDL, UART_BRDL_20M);
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+ serial_port_out(port, UART_BRDH, UART_BRDH_20M);
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+
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+ /* calculate XYD_x and XINCLKDR register */
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+
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+ for (i = 0 ; i < CLOCK_DIV_TAB_ELEMS ; i++) {
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+ denom = (XINDIV_CLOCK/40) / clock_div_tab[i];
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+ nom = (baud * (XYD_Y/40));
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+ xyd_x = ((nom/denom) << 4);
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+ if (xyd_x < XYD_Y) break;
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+ }
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+
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+ serial_port_out(port, UART_XINCLKDR, clock_div_reg[i]);
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+ serial_port_out(port, UART_XYD, (xyd_x<<16) | XYD_Y);
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+
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+ /* unset DLAB */
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+ serial_port_out(port, UART_LCR, up->lcr);
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+
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+ return 0;
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+}
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+
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+EXPORT_SYMBOL_GPL(en7523_set_uart_baud_rate);
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--- a/drivers/tty/serial/8250/8250_of.c
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+++ b/drivers/tty/serial/8250/8250_of.c
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@@ -338,6 +338,7 @@ static const struct of_device_id of_plat
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{ .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
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{ .compatible = "nuvoton,wpcm450-uart", .data = (void *)PORT_NPCM, },
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{ .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, },
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+ { .compatible = "airoha,en7523-uart", .data = (void *)PORT_AIROHA, },
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{ /* end of list */ },
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};
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MODULE_DEVICE_TABLE(of, of_platform_serial_table);
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--- a/drivers/tty/serial/8250/8250_port.c
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+++ b/drivers/tty/serial/8250/8250_port.c
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@@ -330,6 +330,14 @@ static const struct serial8250_config ua
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.rxtrig_bytes = {1, 8, 16, 30},
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.flags = UART_CAP_FIFO | UART_CAP_AFE,
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},
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+ [PORT_AIROHA] = {
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+ .name = "Airoha 16550",
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+ .fifo_size = 8,
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+ .tx_loadsz = 1,
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+ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
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+ .rxtrig_bytes = {1, 4},
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+ .flags = UART_CAP_FIFO,
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+ },
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};
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/* Uart divisor latch read */
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@@ -2880,6 +2888,12 @@ serial8250_do_set_termios(struct uart_po
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serial8250_set_divisor(port, baud, quot, frac);
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+#ifdef CONFIG_SERIAL_8250_AIROHA
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+ /* Airoha SoCs have custom registers for baud rate settings */
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+ if (port->type == PORT_AIROHA)
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+ en7523_set_uart_baud_rate(port, baud);
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+#endif
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+
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/*
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* LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
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* is written without DLAB set, this mode will be disabled.
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--- a/drivers/tty/serial/8250/Makefile
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+++ b/drivers/tty/serial/8250/Makefile
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@@ -46,6 +46,7 @@ obj-$(CONFIG_SERIAL_8250_PERICOM) += 825
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obj-$(CONFIG_SERIAL_8250_PXA) += 8250_pxa.o
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obj-$(CONFIG_SERIAL_8250_TEGRA) += 8250_tegra.o
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obj-$(CONFIG_SERIAL_8250_BCM7271) += 8250_bcm7271.o
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+obj-$(CONFIG_SERIAL_8250_AIROHA) += 8250_en7523.o
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obj-$(CONFIG_SERIAL_OF_PLATFORM) += 8250_of.o
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CFLAGS_8250_ingenic.o += -I$(srctree)/scripts/dtc/libfdt
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--- a/include/uapi/linux/serial_reg.h
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+++ b/include/uapi/linux/serial_reg.h
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@@ -382,5 +382,17 @@
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#define UART_ALTR_EN_TXFIFO_LW 0x01 /* Enable the TX FIFO Low Watermark */
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#define UART_ALTR_TX_LOW 0x41 /* Tx FIFO Low Watermark */
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+/*
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+ * These are definitions for the Airoha EN75XX uart registers
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+ * Normalized because of 32 bits registers.
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+ */
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+#define UART_BRDL 0
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+#define UART_BRDH 1
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+#define UART_XINCLKDR 10
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+#define UART_XYD 11
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+#define UART_TXLVLCNT 12
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+#define UART_RXLVLCNT 13
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+#define UART_FINTLVL 14
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+
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#endif /* _LINUX_SERIAL_REG_H */
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--- a/include/uapi/linux/serial_core.h
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+++ b/include/uapi/linux/serial_core.h
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@@ -45,6 +45,7 @@
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#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
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#define PORT_RT2880 29 /* Ralink RT2880 internal UART */
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#define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */
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+#define PORT_AIROHA 31 /* Airoha 16550 UART */
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/*
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* ARM specific type numbers. These are not currently guaranteed
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--- a/include/linux/serial_8250.h
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+++ b/include/linux/serial_8250.h
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@@ -195,6 +195,7 @@ void serial8250_do_set_mctrl(struct uart
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void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
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unsigned int quot, unsigned int quot_frac);
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int fsl8250_handle_irq(struct uart_port *port);
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+int en7523_set_uart_baud_rate(struct uart_port *port, unsigned int baud);
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int serial8250_handle_irq(struct uart_port *port, unsigned int iir);
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u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr);
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void serial8250_read_char(struct uart_8250_port *up, u16 lsr);
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