mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-11-22 04:56:15 +00:00
9131cb44ff
Introduce EN7581 SoC support with currently rfb board supported. This is a new 64bit SoC from Airoha that is currently almost fully supported upstream with only the DTS missing. Setting source-only waiting for the full upstream support to be completed. Link: https://github.com/openwrt/openwrt/pull/16730 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
33 lines
1.2 KiB
Diff
33 lines
1.2 KiB
Diff
From bc1bb265f504ea19ce611a1aec1a40dec409cd15 Mon Sep 17 00:00:00 2001
|
|
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
|
Date: Wed, 18 Sep 2024 15:32:55 +0200
|
|
Subject: [PATCH 4/4] phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions
|
|
|
|
Fix the following register definitions for REG_CSR_2L_RX{0,1}_REV0
|
|
registers:
|
|
- CSR_2L_PXP_VOS_PNINV
|
|
- CSR_2L_PXP_FE_GAIN_NORMAL_MODE
|
|
- CSR_2L_PXP_FE_GAIN_TRAIN_MODE
|
|
|
|
Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.")
|
|
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
|
---
|
|
drivers/phy/phy-airoha-pcie-regs.h | 6 +++---
|
|
1 file changed, 3 insertions(+), 3 deletions(-)
|
|
|
|
--- a/drivers/phy/phy-airoha-pcie-regs.h
|
|
+++ b/drivers/phy/phy-airoha-pcie-regs.h
|
|
@@ -197,9 +197,9 @@
|
|
#define CSR_2L_PXP_TX1_MULTLANE_EN BIT(0)
|
|
|
|
#define REG_CSR_2L_RX0_REV0 0x00fc
|
|
-#define CSR_2L_PXP_VOS_PNINV GENMASK(3, 2)
|
|
-#define CSR_2L_PXP_FE_GAIN_NORMAL_MODE GENMASK(6, 4)
|
|
-#define CSR_2L_PXP_FE_GAIN_TRAIN_MODE GENMASK(10, 8)
|
|
+#define CSR_2L_PXP_VOS_PNINV GENMASK(19, 18)
|
|
+#define CSR_2L_PXP_FE_GAIN_NORMAL_MODE GENMASK(22, 20)
|
|
+#define CSR_2L_PXP_FE_GAIN_TRAIN_MODE GENMASK(26, 24)
|
|
|
|
#define REG_CSR_2L_RX0_PHYCK_DIV 0x0100
|
|
#define CSR_2L_PXP_RX0_PHYCK_SEL GENMASK(9, 8)
|