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9131cb44ff
Introduce EN7581 SoC support with currently rfb board supported. This is a new 64bit SoC from Airoha that is currently almost fully supported upstream with only the DTS missing. Setting source-only waiting for the full upstream support to be completed. Link: https://github.com/openwrt/openwrt/pull/16730 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
66 lines
2.2 KiB
Diff
66 lines
2.2 KiB
Diff
From bf288bd25d6232310abb81db417376ce460eb032 Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Thu, 27 Jun 2024 13:04:25 +0200
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Subject: [PATCH 3/4] clk: en7523: Remove PCIe reset open drain configuration
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for EN7581
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PCIe reset open drain configuration will be managed by pinctrl driver.
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Link: https://lore.kernel.org/r/43276af5f08a554b4ab2e52e8d437fff5c06a732.1719485847.git.lorenzo@kernel.org
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/clk-en7523.c | 12 ++----------
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1 file changed, 2 insertions(+), 10 deletions(-)
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--- a/drivers/clk/clk-en7523.c
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+++ b/drivers/clk/clk-en7523.c
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@@ -37,8 +37,6 @@
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#define REG_PCIE1_MEM_MASK 0x0c
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#define REG_PCIE2_MEM 0x10
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#define REG_PCIE2_MEM_MASK 0x14
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-#define REG_PCIE_RESET_OPEN_DRAIN 0x018c
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-#define REG_PCIE_RESET_OPEN_DRAIN_MASK GENMASK(2, 0)
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#define REG_NP_SCU_PCIC 0x88
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#define REG_NP_SCU_SSTR 0x9c
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#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
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@@ -86,8 +84,7 @@ struct en_clk_soc_data {
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const u16 *idx_map;
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u16 idx_map_nr;
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} reset;
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- int (*hw_init)(struct platform_device *pdev, void __iomem *base,
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- void __iomem *np_base);
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+ int (*hw_init)(struct platform_device *pdev, void __iomem *np_base);
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};
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static const u32 gsw_base[] = { 400000000, 500000000 };
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@@ -416,7 +413,6 @@ static void en7581_pci_disable(struct cl
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}
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static int en7581_clk_hw_init(struct platform_device *pdev,
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- void __iomem *base,
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void __iomem *np_base)
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{
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void __iomem *pb_base;
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@@ -439,10 +435,6 @@ static int en7581_clk_hw_init(struct pla
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writel(0x28000000, pb_base + REG_PCIE2_MEM);
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writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK);
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- val = readl(base + REG_PCIE_RESET_OPEN_DRAIN);
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- writel(val | REG_PCIE_RESET_OPEN_DRAIN_MASK,
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- base + REG_PCIE_RESET_OPEN_DRAIN);
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-
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return 0;
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}
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@@ -582,7 +574,7 @@ static int en7523_clk_probe(struct platf
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soc_data = device_get_match_data(&pdev->dev);
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if (soc_data->hw_init) {
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- r = soc_data->hw_init(pdev, base, np_base);
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+ r = soc_data->hw_init(pdev, np_base);
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if (r)
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return r;
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}
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