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9131cb44ff
Introduce EN7581 SoC support with currently rfb board supported. This is a new 64bit SoC from Airoha that is currently almost fully supported upstream with only the DTS missing. Setting source-only waiting for the full upstream support to be completed. Link: https://github.com/openwrt/openwrt/pull/16730 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
92 lines
3.1 KiB
Diff
92 lines
3.1 KiB
Diff
From db7a4a11e8be375b0a9c159f688e0cea49eacc5d Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Thu, 27 Jun 2024 13:04:24 +0200
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Subject: [PATCH 2/4] clk: en7523: Remove pcie prepare/unpreare callbacks for
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EN7581 SoC
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Get rid of prepare and unpreare callbacks for PCIe clock since they can
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be modeled as a reset line cosumed by the PCIe driver
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(pcie-mediatek-gen3)
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Link: https://lore.kernel.org/r/16df149975514d3030499c48fc1c64f090093595.1719485847.git.lorenzo@kernel.org
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/clk-en7523.c | 41 ++--------------------------------------
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1 file changed, 2 insertions(+), 39 deletions(-)
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--- a/drivers/clk/clk-en7523.c
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+++ b/drivers/clk/clk-en7523.c
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@@ -366,9 +366,8 @@ static struct clk_hw *en7523_register_pc
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cg->base = np_base;
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cg->hw.init = &init;
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- if (init.ops->disable)
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- init.ops->disable(&cg->hw);
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- init.ops->unprepare(&cg->hw);
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+ if (init.ops->unprepare)
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+ init.ops->unprepare(&cg->hw);
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if (clk_hw_register(dev, &cg->hw))
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return NULL;
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@@ -386,23 +385,6 @@ static int en7581_pci_is_enabled(struct
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return (val & mask) == mask;
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}
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-static int en7581_pci_prepare(struct clk_hw *hw)
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-{
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- struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
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- void __iomem *np_base = cg->base;
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- u32 val, mask;
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-
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- mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
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- REG_RESET_CONTROL_PCIEHB;
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- val = readl(np_base + REG_RESET_CONTROL1);
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- writel(val & ~mask, np_base + REG_RESET_CONTROL1);
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- val = readl(np_base + REG_RESET_CONTROL2);
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- writel(val & ~REG_RESET2_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
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- usleep_range(5000, 10000);
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-
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- return 0;
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-}
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-
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static int en7581_pci_enable(struct clk_hw *hw)
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{
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struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
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@@ -419,23 +401,6 @@ static int en7581_pci_enable(struct clk_
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return 0;
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}
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-static void en7581_pci_unprepare(struct clk_hw *hw)
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-{
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- struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
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- void __iomem *np_base = cg->base;
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- u32 val, mask;
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-
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- mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
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- REG_RESET_CONTROL_PCIEHB;
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- val = readl(np_base + REG_RESET_CONTROL1);
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- writel(val | mask, np_base + REG_RESET_CONTROL1);
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- mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2;
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- writel(val | mask, np_base + REG_RESET_CONTROL1);
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- val = readl(np_base + REG_RESET_CONTROL2);
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- writel(val | REG_RESET_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
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- msleep(100);
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-}
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-
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static void en7581_pci_disable(struct clk_hw *hw)
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{
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struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
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@@ -656,9 +621,7 @@ static const struct en_clk_soc_data en75
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static const struct en_clk_soc_data en7581_data = {
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.pcie_ops = {
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.is_enabled = en7581_pci_is_enabled,
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- .prepare = en7581_pci_prepare,
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.enable = en7581_pci_enable,
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- .unprepare = en7581_pci_unprepare,
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.disable = en7581_pci_disable,
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},
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.reset = {
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