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25c48519cd
This allows us use more easily port en7581 drivers to en7523. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Link: https://github.com/openwrt/openwrt/pull/20365 Signed-off-by: Robert Marko <robimarko@gmail.com>
101 lines
3.1 KiB
Diff
101 lines
3.1 KiB
Diff
From 38195ddfcea372924a68b64f7a6f9235488160be Mon Sep 17 00:00:00 2001
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From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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Date: Sat, 20 Sep 2025 03:57:25 +0300
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Subject: [PATCH 1/3] dt-bindings: clock: airoha: Add reset support to EN7523
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clock binding
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Introduce reset capability to EN7523 device-tree clock binding
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documentation.
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Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
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---
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.../bindings/clock/airoha,en7523-scu.yaml | 3 +-
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.../dt-bindings/reset/airoha,en7523-reset.h | 61 +++++++++++++++++++
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2 files changed, 62 insertions(+), 2 deletions(-)
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create mode 100644 include/dt-bindings/reset/airoha,en7523-reset.h
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--- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
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+++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
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@@ -64,8 +64,6 @@ allOf:
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- description: scu base address
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- description: misc scu base address
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- '#reset-cells': false
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-
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- if:
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properties:
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compatible:
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@@ -89,6 +87,7 @@ examples:
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reg = <0x1fa20000 0x400>,
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<0x1fb00000 0x1000>;
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#clock-cells = <1>;
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+ #reset-cells = <1>;
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};
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- |
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--- /dev/null
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+++ b/include/dt-bindings/reset/airoha,en7523-reset.h
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@@ -0,0 +1,61 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+/*
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+ * Copyright (C) 2024 iopsys Software Solutions AB.
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+ * Copyright (C) 2025 Genexis AB.
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+ *
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+ * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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+ *
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+ * based on
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+ * include/dt-bindings/reset/airoha,en7581-reset.h
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+ * by Lorenzo Bianconi <lorenzo@kernel.org>
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+ */
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+
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+#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7523_H_
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+#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7523_H_
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+
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+/* RST_CTRL2 */
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+#define EN7523_XPON_PHY_RST 0
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+#define EN7523_XSI_MAC_RST 1
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+#define EN7523_XSI_PHY_RST 2
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+#define EN7523_NPU_RST 3
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+#define EN7523_I2S_RST 4
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+#define EN7523_TRNG_RST 5
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+#define EN7523_TRNG_MSTART_RST 6
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+#define EN7523_DUAL_HSI0_RST 7
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+#define EN7523_DUAL_HSI1_RST 8
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+#define EN7523_HSI_RST 9
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+#define EN7523_DUAL_HSI0_MAC_RST 10
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+#define EN7523_DUAL_HSI1_MAC_RST 11
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+#define EN7523_HSI_MAC_RST 12
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+#define EN7523_WDMA_RST 13
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+#define EN7523_WOE0_RST 14
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+#define EN7523_WOE1_RST 15
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+#define EN7523_HSDMA_RST 16
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+#define EN7523_I2C2RBUS_RST 17
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+#define EN7523_TDMA_RST 18
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+/* RST_CTRL1 */
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+#define EN7523_PCM1_ZSI_ISI_RST 19
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+#define EN7523_FE_PDMA_RST 20
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+#define EN7523_FE_QDMA_RST 21
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+#define EN7523_PCM_SPIWP_RST 22
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+#define EN7523_CRYPTO_RST 23
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+#define EN7523_TIMER_RST 24
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+#define EN7523_PCM1_RST 25
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+#define EN7523_UART_RST 26
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+#define EN7523_GPIO_RST 27
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+#define EN7523_GDMA_RST 28
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+#define EN7523_I2C_MASTER_RST 29
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+#define EN7523_PCM2_ZSI_ISI_RST 30
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+#define EN7523_SFC_RST 31
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+#define EN7523_UART2_RST 32
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+#define EN7523_GDMP_RST 33
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+#define EN7523_FE_RST 34
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+#define EN7523_USB_HOST_P0_RST 35
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+#define EN7523_GSW_RST 36
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+#define EN7523_SFC2_PCM_RST 37
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+#define EN7523_PCIE0_RST 38
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+#define EN7523_PCIE1_RST 39
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+#define EN7523_PCIE_HB_RST 40
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+#define EN7523_XPON_MAC_RST 41
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+
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+#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7523_H_ */
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