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	Introduce initial support for Airoha AN7583 SoC and add all the required patch for basic functionality of the SoC. Airoha AN7583 is based on Airoha EN7581 SoC with some major changes on the PHY handling and Serdes. It can be see as a lower spec of EN7581 with modern and simplified implementations. All the patch are sent upstream and are pending revision. Support for PCIe and USB will come later as soon as DT structure is accepted upstream. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
		
			
				
	
	
		
			123 lines
		
	
	
		
			3.8 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			123 lines
		
	
	
		
			3.8 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| From 12838dd20851a6eae67061c5f195f31981a4d8c1 Mon Sep 17 00:00:00 2001
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| From: Christian Marangi <ansuelsmth@gmail.com>
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| Date: Wed, 28 May 2025 02:39:35 +0200
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| Subject: [PATCH 09/10] dt-bindings: clock: airoha: Document support for AN7583
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|  clock
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| 
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| Document support for Airoha AN7583 clock. This is based on the EN7523
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| clock schema with the new requirement of the "airoha,chip-scu"
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| (previously optional for EN7581).
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| 
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| Add additional binding for additional clock and reset lines.
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| 
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| Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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| ---
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|  .../bindings/clock/airoha,en7523-scu.yaml     |  9 +++
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|  include/dt-bindings/clock/en7523-clk.h        |  3 +
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|  .../dt-bindings/reset/airoha,an7583-reset.h   | 61 +++++++++++++++++++
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|  3 files changed, 73 insertions(+)
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|  create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h
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| 
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| # diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
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| # index bce77a14c938..be9759b86fdc 100644
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| # --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
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| # +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
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| # @@ -32,6 +32,7 @@ properties:
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| #        - enum:
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| #            - airoha,en7523-scu
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| #            - airoha,en7581-scu
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| # +          - airoha,an7583-scu
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|  
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| #    reg:
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| #      items:
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| # @@ -82,6 +83,14 @@ allOf:
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| #          reg:
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| #            maxItems: 1
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|  
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| # +  - if:
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| # +      properties:
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| # +        compatible:
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| # +          const: airoha,an7583-scu
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| # +    then:
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| # +      required:
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| # +        - airoha,chip-scu
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| # +
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| #  additionalProperties: false
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|  
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| #  examples:
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| --- a/include/dt-bindings/clock/en7523-clk.h
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| +++ b/include/dt-bindings/clock/en7523-clk.h
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| @@ -14,4 +14,7 @@
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|  
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|  #define EN7581_CLK_EMMC		8
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|  
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| +#define AN7583_CLK_MDIO0	9
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| +#define AN7583_CLK_MDIO1	10
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| +
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|  #endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */
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| --- /dev/null
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| +++ b/include/dt-bindings/reset/airoha,an7583-reset.h
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| @@ -0,0 +1,62 @@
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| +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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| +/*
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| + * Copyright (c) 2024 AIROHA Inc
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| + * Author: Christian Marangi <ansuelsmth@gmail.com>
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| + */
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| +
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| +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_
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| +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_
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| +
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| +/* RST_CTRL2 */
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| +#define AN7583_XPON_PHY_RST		 0
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| +#define AN7583_GPON_OLT_RST		 1
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| +#define AN7583_CPU_TIMER2_RST		 2
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| +#define AN7583_HSUART_RST		 3
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| +#define AN7583_UART4_RST		 4
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| +#define AN7583_UART5_RST		 5
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| +#define AN7583_I2C2_RST			 6
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| +#define AN7583_XSI_MAC_RST		 7
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| +#define AN7583_XSI_PHY_RST		 8
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| +#define AN7583_NPU_RST			 9
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| +#define AN7583_TRNG_MSTART_RST		10
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| +#define AN7583_DUAL_HSI0_RST		11
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| +#define AN7583_DUAL_HSI1_RST		12
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| +#define AN7583_DUAL_HSI0_MAC_RST	13
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| +#define AN7583_DUAL_HSI1_MAC_RST	14
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| +#define AN7583_XPON_XFI_RST     	15
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| +#define AN7583_WDMA_RST			16
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| +#define AN7583_WOE0_RST			17
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| +#define AN7583_HSDMA_RST		18
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| +#define AN7583_TDMA_RST			19
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| +#define AN7583_EMMC_RST			20
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| +#define AN7583_SOE_RST			21
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| +#define AN7583_XFP_MAC_RST		22
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| +#define AN7583_MDIO0                    23
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| +#define AN7583_MDIO1                    24
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| +/* RST_CTRL1 */
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| +#define AN7583_PCM1_ZSI_ISI_RST		25
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| +#define AN7583_FE_PDMA_RST		26
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| +#define AN7583_FE_QDMA_RST		27
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| +#define AN7583_PCM_SPIWP_RST		28
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| +#define AN7583_CRYPTO_RST		29
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| +#define AN7583_TIMER_RST		30
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| +#define AN7583_PCM1_RST			31
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| +#define AN7583_UART_RST			32
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| +#define AN7583_GPIO_RST			33
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| +#define AN7583_GDMA_RST			34
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| +#define AN7583_I2C_MASTER_RST		35
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| +#define AN7583_PCM2_ZSI_ISI_RST		36
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| +#define AN7583_SFC_RST			37
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| +#define AN7583_UART2_RST		38
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| +#define AN7583_GDMP_RST			39
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| +#define AN7583_FE_RST			40
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| +#define AN7583_USB_HOST_P0_RST		41
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| +#define AN7583_GSW_RST			42
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| +#define AN7583_SFC2_PCM_RST		43
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| +#define AN7583_PCIE0_RST		44
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| +#define AN7583_PCIE1_RST		45
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| +#define AN7583_CPU_TIMER_RST		46
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| +#define AN7583_PCIE_HB_RST		47
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| +#define AN7583_XPON_MAC_RST		48
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| +
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| +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ */
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