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c5b12fc02a
Introduce initial support for Airoha AN7583 SoC and add all the required patch for basic functionality of the SoC. Airoha AN7583 is based on Airoha EN7581 SoC with some major changes on the PHY handling and Serdes. It can be see as a lower spec of EN7581 with modern and simplified implementations. All the patch are sent upstream and are pending revision. Support for PCIe and USB will come later as soon as DT structure is accepted upstream. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
141 lines
4.7 KiB
Diff
141 lines
4.7 KiB
Diff
From 7e112e51d48db09739dd73c90411fc8a5635747f Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 22 May 2025 15:13:10 +0200
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Subject: [PATCH 2/3] net: dsa: mt7530: Add AN7583 support
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Add Airoha AN7583 Switch support. This is based on Airoha EN7581 that is
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based on Mediatek MT7988 Switch.
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Airoha AN7583 require additional tweak to the GEPHY_CONN_CFG register to
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make the internal PHY work.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/net/dsa/mt7530-mmio.c | 1 +
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drivers/net/dsa/mt7530.c | 24 ++++++++++++++++++++++--
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drivers/net/dsa/mt7530.h | 18 ++++++++++++++----
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3 files changed, 37 insertions(+), 6 deletions(-)
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--- a/drivers/net/dsa/mt7530-mmio.c
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+++ b/drivers/net/dsa/mt7530-mmio.c
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@@ -11,6 +11,7 @@
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#include "mt7530.h"
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static const struct of_device_id mt7988_of_match[] = {
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+ { .compatible = "airoha,an7583-switch", .data = &mt753x_table[ID_AN7583], },
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{ .compatible = "airoha,en7581-switch", .data = &mt753x_table[ID_EN7581], },
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{ .compatible = "mediatek,mt7988-switch", .data = &mt753x_table[ID_MT7988], },
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{ /* sentinel */ },
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -1153,7 +1153,7 @@ mt753x_cpu_port_enable(struct dsa_switch
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* is affine to the inbound user port.
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*/
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if (priv->id == ID_MT7531 || priv->id == ID_MT7988 ||
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- priv->id == ID_EN7581)
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+ priv->id == ID_EN7581 || priv->id == ID_AN7583)
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mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port)));
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/* CPU port gets connected to all user ports of
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@@ -2589,7 +2589,7 @@ mt7531_setup_common(struct dsa_switch *d
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mt7530_set(priv, MT753X_AGC, LOCAL_EN);
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/* Enable Special Tag for rx frames */
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- if (priv->id == ID_EN7581)
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+ if (priv->id == ID_EN7581 || priv->id == ID_AN7583)
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mt7530_write(priv, MT753X_CPORT_SPTAG_CFG,
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CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN);
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@@ -3157,6 +3157,16 @@ static int mt7988_setup(struct dsa_switc
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reset_control_deassert(priv->rstc);
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usleep_range(20, 50);
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+ /* AN7583 require additional tweak to CONN_CFG */
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+ if (priv->id == ID_AN7583)
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+ mt7530_rmw(priv, AN7583_GEPHY_CONN_CFG,
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+ AN7583_CSR_DPHY_CKIN_SEL |
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+ AN7583_CSR_PHY_CORE_REG_CLK_SEL |
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+ AN7583_CSR_ETHER_AFE_PWD,
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+ AN7583_CSR_DPHY_CKIN_SEL |
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+ AN7583_CSR_PHY_CORE_REG_CLK_SEL |
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+ FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0));
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+
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/* Reset the switch PHYs */
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mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);
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@@ -3253,6 +3263,16 @@ const struct mt753x_info mt753x_table[]
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.pcs_ops = &mt7530_pcs_ops,
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.sw_setup = mt7988_setup,
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.phy_read_c22 = mt7531_ind_c22_phy_read,
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+ .phy_write_c22 = mt7531_ind_c22_phy_write,
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+ .phy_read_c45 = mt7531_ind_c45_phy_read,
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+ .phy_write_c45 = mt7531_ind_c45_phy_write,
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+ .mac_port_get_caps = en7581_mac_port_get_caps,
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+ },
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+ [ID_AN7583] = {
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+ .id = ID_AN7583,
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+ .pcs_ops = &mt7530_pcs_ops,
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+ .sw_setup = mt7988_setup,
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+ .phy_read_c22 = mt7531_ind_c22_phy_read,
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.phy_write_c22 = mt7531_ind_c22_phy_write,
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.phy_read_c45 = mt7531_ind_c45_phy_read,
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.phy_write_c45 = mt7531_ind_c45_phy_write,
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--- a/drivers/net/dsa/mt7530.h
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+++ b/drivers/net/dsa/mt7530.h
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@@ -20,6 +20,7 @@ enum mt753x_id {
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ID_MT7531 = 2,
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ID_MT7988 = 3,
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ID_EN7581 = 4,
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+ ID_AN7583 = 5,
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};
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#define NUM_TRGMII_CTRL 5
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@@ -66,7 +67,8 @@ enum mt753x_id {
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#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \
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id == ID_MT7988 || \
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- id == ID_EN7581) ? \
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+ id == ID_EN7581 || \
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+ id == ID_AN7583) ? \
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MT7531_CFC : MT753X_MFC)
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#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \
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@@ -76,19 +78,22 @@ enum mt753x_id {
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#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \
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id == ID_MT7988 || \
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- id == ID_EN7581) ? \
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+ id == ID_EN7581 || \
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+ id == ID_AN7583) ? \
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MT7531_MIRROR_PORT_MASK : \
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MT7530_MIRROR_PORT_MASK)
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#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \
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id == ID_MT7988 || \
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- id == ID_EN7581) ? \
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+ id == ID_EN7581 || \
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+ id == ID_AN7583) ? \
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MT7531_MIRROR_PORT_GET(val) : \
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MT7530_MIRROR_PORT_GET(val))
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#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \
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id == ID_MT7988 || \
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- id == ID_EN7581) ? \
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+ id == ID_EN7581 || \
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+ id == ID_AN7583) ? \
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MT7531_MIRROR_PORT_SET(val) : \
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MT7530_MIRROR_PORT_SET(val))
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@@ -619,6 +624,11 @@ enum mt7531_xtal_fsel {
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#define CPORT_SW2FE_STAG_EN BIT(1)
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#define CPORT_FE2SW_STAG_EN BIT(0)
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+#define AN7583_GEPHY_CONN_CFG 0x7c14
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+#define AN7583_CSR_DPHY_CKIN_SEL BIT(31)
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+#define AN7583_CSR_PHY_CORE_REG_CLK_SEL BIT(30)
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+#define AN7583_CSR_ETHER_AFE_PWD GENMASK(28, 24)
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+
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/* Registers for LED GPIO control (MT7530 only)
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* All registers follow this pattern:
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* [ 2: 0] port 0
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