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7afc2da3fc
Add pending patch for USB support on AN7581 SoC. This is also required to make operational the 3rd PCIe line that use the USB2 Serdes for PCIe operations. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
35 lines
1.2 KiB
Diff
35 lines
1.2 KiB
Diff
From 112c6ea7ac356dab16e11084f2183e653a289e91 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Tue, 28 Oct 2025 12:35:41 +0100
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Subject: [PATCH 10/10] PCI: mediatek-gen3: set PHY mode for Airoha EN7581
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For the Airoha EN7581 SoC, the 3rd PCIe line is attached to a special
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PHY that can be both used for USB 3.0 operation or PCIe.
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Configure the PHY for PCIe operation before init it to correctly
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configure the SCU Serdes register.
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This permits correct functionality and enumeration of PCIe devices on
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the 3rd PCIe line present on the SoC.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/pci/controller/pcie-mediatek-gen3.c | 6 ++++++
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1 file changed, 6 insertions(+)
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--- a/drivers/pci/controller/pcie-mediatek-gen3.c
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+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
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@@ -925,6 +925,12 @@ static int mtk_pcie_en7581_power_up(stru
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size = lower_32_bits(resource_size(entry->res));
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regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));
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+ err = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
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+ if (err) {
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+ dev_err(dev, "failed to set PHY mode\n");
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+ return err;
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+ }
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+
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/*
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* Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
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* requires PHY initialization and power-on before PHY reset deassert.
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