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39ae0f972d
This is an automatically generated commit. When doing `git bisect`, consider `git bisect --skip`. Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me> Link: https://github.com/openwrt/openwrt/pull/19038 Signed-off-by: Robert Marko <robimarko@gmail.com>
102 lines
3.7 KiB
Diff
102 lines
3.7 KiB
Diff
From e0758a8694fbaffdc72940774db295585e951119 Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Fri, 28 Feb 2025 11:54:11 +0100
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Subject: [PATCH 03/15] net: airoha: Move reg/write utility routines in
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airoha_eth.h
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This is a preliminary patch to introduce flowtable hw offloading
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support for airoha_eth driver.
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/ethernet/airoha/airoha_eth.c | 28 +++---------------------
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drivers/net/ethernet/airoha/airoha_eth.h | 26 ++++++++++++++++++++++
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2 files changed, 29 insertions(+), 25 deletions(-)
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--- a/drivers/net/ethernet/airoha/airoha_eth.c
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+++ b/drivers/net/ethernet/airoha/airoha_eth.c
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@@ -673,17 +673,17 @@ struct airoha_qdma_fwd_desc {
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__le32 rsv1;
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};
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-static u32 airoha_rr(void __iomem *base, u32 offset)
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+u32 airoha_rr(void __iomem *base, u32 offset)
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{
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return readl(base + offset);
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}
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-static void airoha_wr(void __iomem *base, u32 offset, u32 val)
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+void airoha_wr(void __iomem *base, u32 offset, u32 val)
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{
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writel(val, base + offset);
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}
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-static u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
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+u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
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{
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val |= (airoha_rr(base, offset) & ~mask);
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airoha_wr(base, offset, val);
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@@ -691,28 +691,6 @@ static u32 airoha_rmw(void __iomem *base
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return val;
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}
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-#define airoha_fe_rr(eth, offset) \
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- airoha_rr((eth)->fe_regs, (offset))
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-#define airoha_fe_wr(eth, offset, val) \
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- airoha_wr((eth)->fe_regs, (offset), (val))
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-#define airoha_fe_rmw(eth, offset, mask, val) \
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- airoha_rmw((eth)->fe_regs, (offset), (mask), (val))
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-#define airoha_fe_set(eth, offset, val) \
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- airoha_rmw((eth)->fe_regs, (offset), 0, (val))
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-#define airoha_fe_clear(eth, offset, val) \
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- airoha_rmw((eth)->fe_regs, (offset), (val), 0)
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-
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-#define airoha_qdma_rr(qdma, offset) \
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- airoha_rr((qdma)->regs, (offset))
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-#define airoha_qdma_wr(qdma, offset, val) \
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- airoha_wr((qdma)->regs, (offset), (val))
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-#define airoha_qdma_rmw(qdma, offset, mask, val) \
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- airoha_rmw((qdma)->regs, (offset), (mask), (val))
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-#define airoha_qdma_set(qdma, offset, val) \
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- airoha_rmw((qdma)->regs, (offset), 0, (val))
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-#define airoha_qdma_clear(qdma, offset, val) \
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- airoha_rmw((qdma)->regs, (offset), (val), 0)
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-
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static void airoha_qdma_set_irqmask(struct airoha_qdma *qdma, int index,
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u32 clear, u32 set)
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{
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--- a/drivers/net/ethernet/airoha/airoha_eth.h
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+++ b/drivers/net/ethernet/airoha/airoha_eth.h
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@@ -248,4 +248,30 @@ struct airoha_eth {
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struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS];
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};
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+u32 airoha_rr(void __iomem *base, u32 offset);
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+void airoha_wr(void __iomem *base, u32 offset, u32 val);
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+u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
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+
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+#define airoha_fe_rr(eth, offset) \
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+ airoha_rr((eth)->fe_regs, (offset))
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+#define airoha_fe_wr(eth, offset, val) \
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+ airoha_wr((eth)->fe_regs, (offset), (val))
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+#define airoha_fe_rmw(eth, offset, mask, val) \
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+ airoha_rmw((eth)->fe_regs, (offset), (mask), (val))
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+#define airoha_fe_set(eth, offset, val) \
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+ airoha_rmw((eth)->fe_regs, (offset), 0, (val))
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+#define airoha_fe_clear(eth, offset, val) \
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+ airoha_rmw((eth)->fe_regs, (offset), (val), 0)
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+
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+#define airoha_qdma_rr(qdma, offset) \
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+ airoha_rr((qdma)->regs, (offset))
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+#define airoha_qdma_wr(qdma, offset, val) \
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+ airoha_wr((qdma)->regs, (offset), (val))
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+#define airoha_qdma_rmw(qdma, offset, mask, val) \
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+ airoha_rmw((qdma)->regs, (offset), (mask), (val))
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+#define airoha_qdma_set(qdma, offset, val) \
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+ airoha_rmw((qdma)->regs, (offset), 0, (val))
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+#define airoha_qdma_clear(qdma, offset, val) \
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+ airoha_rmw((qdma)->regs, (offset), (val), 0)
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+
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#endif /* AIROHA_ETH_H */
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