mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2025-10-31 16:15:54 +00:00
d62ecd6c07
Refresh patches 6.12 for airoha and econet Fixes:122135b964("airoha: an7581: add support for kernel 6.12") Fixes:73d0f92460("kernel: Add new platform EcoNet MIPS") Signed-off-by: Leo Barsky <leobrsky@proton.me> Link: https://github.com/openwrt/openwrt/pull/20073 Signed-off-by: Robert Marko <robimarko@gmail.com>
85 lines
2.7 KiB
Diff
85 lines
2.7 KiB
Diff
From a9eaf305017a5ebe73ab34e85bd5414055a88f29 Mon Sep 17 00:00:00 2001
|
|
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
|
Date: Tue, 12 Nov 2024 01:08:54 +0100
|
|
Subject: [PATCH 6/6] clk: en7523: map io region in a single block
|
|
|
|
Map all clock-controller memory region in a single block.
|
|
This patch does not introduce any backward incompatibility since the dts
|
|
for EN7581 SoC is not upstream yet.
|
|
|
|
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
|
Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-7-8ada5e394ae4@kernel.org
|
|
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
---
|
|
drivers/clk/clk-en7523.c | 32 +++++++++++++-------------------
|
|
1 file changed, 13 insertions(+), 19 deletions(-)
|
|
|
|
--- a/drivers/clk/clk-en7523.c
|
|
+++ b/drivers/clk/clk-en7523.c
|
|
@@ -39,8 +39,8 @@
|
|
#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
|
|
#define REG_CRYPTO_CLKSRC2 0x20c
|
|
|
|
-#define REG_RST_CTRL2 0x00
|
|
-#define REG_RST_CTRL1 0x04
|
|
+#define REG_RST_CTRL2 0x830
|
|
+#define REG_RST_CTRL1 0x834
|
|
|
|
struct en_clk_desc {
|
|
int id;
|
|
@@ -646,15 +646,9 @@ static const struct reset_control_ops en
|
|
.status = en7523_reset_status,
|
|
};
|
|
|
|
-static int en7581_reset_register(struct platform_device *pdev)
|
|
+static int en7581_reset_register(struct device *dev, void __iomem *base)
|
|
{
|
|
- struct device *dev = &pdev->dev;
|
|
struct en_rst_data *rst_data;
|
|
- void __iomem *base;
|
|
-
|
|
- base = devm_platform_ioremap_resource(pdev, 1);
|
|
- if (IS_ERR(base))
|
|
- return PTR_ERR(base);
|
|
|
|
rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
|
|
if (!rst_data)
|
|
@@ -678,27 +672,27 @@ static int en7581_reset_register(struct
|
|
static int en7581_clk_hw_init(struct platform_device *pdev,
|
|
struct clk_hw_onecell_data *clk_data)
|
|
{
|
|
- void __iomem *np_base;
|
|
struct regmap *map;
|
|
+ void __iomem *base;
|
|
u32 val;
|
|
|
|
map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
|
|
if (IS_ERR(map))
|
|
return PTR_ERR(map);
|
|
|
|
- np_base = devm_platform_ioremap_resource(pdev, 0);
|
|
- if (IS_ERR(np_base))
|
|
- return PTR_ERR(np_base);
|
|
+ base = devm_platform_ioremap_resource(pdev, 0);
|
|
+ if (IS_ERR(base))
|
|
+ return PTR_ERR(base);
|
|
|
|
- en7581_register_clocks(&pdev->dev, clk_data, map, np_base);
|
|
+ en7581_register_clocks(&pdev->dev, clk_data, map, base);
|
|
|
|
- val = readl(np_base + REG_NP_SCU_SSTR);
|
|
+ val = readl(base + REG_NP_SCU_SSTR);
|
|
val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
|
|
- writel(val, np_base + REG_NP_SCU_SSTR);
|
|
- val = readl(np_base + REG_NP_SCU_PCIC);
|
|
- writel(val | 3, np_base + REG_NP_SCU_PCIC);
|
|
+ writel(val, base + REG_NP_SCU_SSTR);
|
|
+ val = readl(base + REG_NP_SCU_PCIC);
|
|
+ writel(val | 3, base + REG_NP_SCU_PCIC);
|
|
|
|
- return en7581_reset_register(pdev);
|
|
+ return en7581_reset_register(&pdev->dev, base);
|
|
}
|
|
|
|
static int en7523_clk_probe(struct platform_device *pdev)
|