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	This patch series greatly improve airoha snfi driver and fix a number of serious bugs. Fixed bugs: * Fix reading/writing of flashes with more than one plane per lun * Fill the buffer with 0xff before writing * Fix reading of flashes supporting continuous reading mode * Fix error paths Improvements: * Add support of dual/quad wires spi modes in exec_op(). This also fix flash reading/writing if dirmap can't be created. * Support of dualio/quadio flash reading commands Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Link: https://github.com/openwrt/openwrt/pull/20295 Signed-off-by: Robert Marko <robimarko@gmail.com>
		
			
				
	
	
		
			93 lines
		
	
	
		
			3.0 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			93 lines
		
	
	
		
			3.0 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| From baaba9b8d3d907575323cbb7fabeae23db2a542b Mon Sep 17 00:00:00 2001
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| From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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| Date: Mon, 11 Aug 2025 20:52:34 +0300
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| Subject: [PATCH v6 08/13] spi: airoha: support of dualio/quadio flash reading
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|  commands
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| 
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| Airoha snfi spi controller supports acceleration of DUAL/QUAD
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| operations, but does not supports DUAL_IO/QUAD_IO operations.
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| Luckily DUAL/QUAD operations do the same as DUAL_IO/QUAD_IO ones,
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| so we can issue corresponding DUAL/QUAD operation instead of
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| DUAL_IO/QUAD_IO one.
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| 
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| Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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| Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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| ---
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|  drivers/spi/spi-airoha-snfi.c | 28 ++++++++++++++++++++++------
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|  1 file changed, 22 insertions(+), 6 deletions(-)
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| 
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| --- a/drivers/spi/spi-airoha-snfi.c
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| +++ b/drivers/spi/spi-airoha-snfi.c
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| @@ -147,6 +147,8 @@
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|  #define SPI_NFI_CUS_SEC_SIZE_EN			BIT(16)
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|  
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|  #define REG_SPI_NFI_RD_CTL2			0x0510
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| +#define SPI_NFI_DATA_READ_CMD			GENMASK(7, 0)
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| +
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|  #define REG_SPI_NFI_RD_CTL3			0x0514
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|  
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|  #define REG_SPI_NFI_PG_CTL1			0x0524
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| @@ -179,7 +181,9 @@
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|  #define SPI_NAND_OP_READ_FROM_CACHE_SINGLE	0x03
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|  #define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST	0x0b
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|  #define SPI_NAND_OP_READ_FROM_CACHE_DUAL	0x3b
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| +#define SPI_NAND_OP_READ_FROM_CACHE_DUALIO	0xbb
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|  #define SPI_NAND_OP_READ_FROM_CACHE_QUAD	0x6b
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| +#define SPI_NAND_OP_READ_FROM_CACHE_QUADIO	0xeb
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|  #define SPI_NAND_OP_WRITE_ENABLE		0x06
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|  #define SPI_NAND_OP_WRITE_DISABLE		0x04
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|  #define SPI_NAND_OP_PROGRAM_LOAD_SINGLE		0x02
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| @@ -664,26 +668,38 @@ static int airoha_snand_dirmap_create(st
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|  static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
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|  					u64 offs, size_t len, void *buf)
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|  {
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| -	struct spi_mem_op *op = &desc->info.op_tmpl;
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|  	struct spi_device *spi = desc->mem->spi;
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|  	struct airoha_snand_ctrl *as_ctrl;
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|  	u8 *txrx_buf = spi_get_ctldata(spi);
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|  	dma_addr_t dma_addr;
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| -	u32 val, rd_mode;
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| +	u32 val, rd_mode, opcode;
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|  	int err;
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|  
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|  	as_ctrl = spi_controller_get_devdata(spi->controller);
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|  
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| -	switch (op->cmd.opcode) {
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| +	/*
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| +	 * DUALIO and QUADIO opcodes are not supported by the spi controller,
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| +	 * replace them with supported opcodes.
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| +	 */
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| +	opcode = desc->info.op_tmpl.cmd.opcode;
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| +	switch (opcode) {
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| +	case SPI_NAND_OP_READ_FROM_CACHE_SINGLE:
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| +	case SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST:
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| +		rd_mode = 0;
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| +		break;
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|  	case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
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| +	case SPI_NAND_OP_READ_FROM_CACHE_DUALIO:
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| +		opcode = SPI_NAND_OP_READ_FROM_CACHE_DUAL;
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|  		rd_mode = 1;
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|  		break;
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|  	case SPI_NAND_OP_READ_FROM_CACHE_QUAD:
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| +	case SPI_NAND_OP_READ_FROM_CACHE_QUADIO:
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| +		opcode = SPI_NAND_OP_READ_FROM_CACHE_QUAD;
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|  		rd_mode = 2;
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|  		break;
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|  	default:
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| -		rd_mode = 0;
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| -		break;
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| +		/* unknown opcode */
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| +		return -EOPNOTSUPP;
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|  	}
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|  
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|  	err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
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| @@ -717,7 +733,7 @@ static ssize_t airoha_snand_dirmap_read(
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|  
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|  	/* set read command */
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|  	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL2,
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| -			   op->cmd.opcode);
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| +			   FIELD_PREP(SPI_NFI_DATA_READ_CMD, opcode));
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|  	if (err)
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|  		goto error_dma_unmap;
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|  
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