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e60729c720
Upgrade the u-boot to a more recent version, and drop and refresh patches while at it. Additionally, use the correct architecture when running mkimage. Runtime-tested: - SiFive Unleashed - SiFive Unmatched Dropped: 0009-riscv-Fix-build-against-binutils.patch Added: 0006-riscv-sifive-fu740-reduce-DDR-speed-from-1866MT-s-to.patch Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
38 lines
1.2 KiB
Diff
38 lines
1.2 KiB
Diff
From 9b2868e9fda750c985313a40e60b67f96dc77ed1 Mon Sep 17 00:00:00 2001
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From: Atish Patra <atish.patra@wdc.com>
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Date: Mon, 25 Oct 2021 11:35:41 -0700
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Subject: [PATCH 5/5] riscv: dts: Add few PMU events
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fu740 has 2 HPM counters and many HPM events defined in the fu740 manual[1].
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This patch adds some of these events and their mapping as per the
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OpenSBI PMU DT binding for now.
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[1]https://sifive.cdn.prismic.io/sifive/de1491e5-077c-461d-9605-e8a0ce57337d_fu740-c000-manual-v1p3.pdf
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Upstream-Status: Pending
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Signed-off-by: Atish Patra <atish.patra@wdc.com>
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---
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arch/riscv/dts/fu740-c000.dtsi | 11 +++++++++++
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1 file changed, 11 insertions(+)
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--- a/arch/riscv/dts/fu740-c000.dtsi
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+++ b/arch/riscv/dts/fu740-c000.dtsi
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@@ -140,6 +140,17 @@
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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+ pmu {
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+ compatible = "riscv,pmu";
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+ riscv,raw-event-to-mhpmcounters = <0x00000000 0x200 0x18
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+ 0x00000000 0x400 0x18
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+ 0x00000000 0x800 0x18>;
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+ riscv,event-to-mhpmcounters = <0x05 0x06 0x18
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+ 0x10009 0x10009 0x18>;
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+ riscv,event-to-mhpmevent = <0x05 0x00000000 0x4000
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+ 0x06 0x00000000 0x4001
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+ 0x10008 0x00000000 0x102>;
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+ };
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plic0: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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