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d41d9befb9
Add u-boot bootloader based on 2023.01 to support D1-based boards, currently: - Dongshan Nezha STU - LicheePi RV Dock - MangoPi MQ-Pro - Nezha D1 Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
394 lines
12 KiB
Diff
394 lines
12 KiB
Diff
From 73d6c82e34e89cfde880d1948b3e0dc714adead8 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sat, 30 Apr 2022 22:34:19 -0500
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Subject: [PATCH 11/90] clk: sunxi: Add support for the D1 CCU
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Since the D1 CCU binding is defined, we can add support for its
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gates/resets, following the pattern of the existing drivers.
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Series-to: sunxi
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/clk/sunxi/Kconfig | 6 +
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drivers/clk/sunxi/Makefile | 1 +
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drivers/clk/sunxi/clk_d1.c | 82 ++++++++++++
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drivers/clk/sunxi/clk_sunxi.c | 5 +
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include/dt-bindings/clock/sun20i-d1-ccu.h | 156 ++++++++++++++++++++++
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include/dt-bindings/reset/sun20i-d1-ccu.h | 77 +++++++++++
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6 files changed, 327 insertions(+)
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create mode 100644 drivers/clk/sunxi/clk_d1.c
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create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h
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create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h
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--- a/drivers/clk/sunxi/Kconfig
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+++ b/drivers/clk/sunxi/Kconfig
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@@ -87,6 +87,12 @@ config CLK_SUN8I_H3
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This enables common clock driver support for platforms based
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on Allwinner H3/H5 SoC.
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+config CLK_SUN20I_D1
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+ bool "Clock driver for Allwinner D1"
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+ help
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+ This enables common clock driver support for platforms based
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+ on Allwinner D1 SoC.
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+
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config CLK_SUN50I_H6
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bool "Clock driver for Allwinner H6"
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default MACH_SUN50I_H6
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--- a/drivers/clk/sunxi/Makefile
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+++ b/drivers/clk/sunxi/Makefile
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@@ -19,6 +19,7 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
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obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
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obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
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obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
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+obj-$(CONFIG_CLK_SUN20I_D1) += clk_d1.o
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obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
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obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
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obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
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--- /dev/null
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+++ b/drivers/clk/sunxi/clk_d1.c
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@@ -0,0 +1,82 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
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+ */
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+
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+#include <common.h>
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+#include <clk-uclass.h>
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+#include <dm.h>
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+#include <errno.h>
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+#include <clk/sunxi.h>
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+#include <dt-bindings/clock/sun20i-d1-ccu.h>
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+#include <dt-bindings/reset/sun20i-d1-ccu.h>
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+#include <linux/bitops.h>
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+
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+static struct ccu_clk_gate d1_gates[] = {
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+ [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
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+ [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
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+ [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
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+ [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
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+ [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
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+ [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
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+ [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
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+ [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
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+ [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
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+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
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+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
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+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
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+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
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+ [CLK_SPI0] = GATE(0x940, BIT(31)),
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+ [CLK_SPI1] = GATE(0x944, BIT(31)),
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+ [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
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+ [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
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+
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+ [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
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+
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+ [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
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+ [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
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+ [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
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+ [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
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+ [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
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+ [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
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+ [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
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+ [CLK_BUS_LRADC] = GATE(0xa9c, BIT(0)),
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+
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+ [CLK_RISCV] = GATE(0xd04, BIT(31)),
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+};
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+
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+static struct ccu_reset d1_resets[] = {
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+ [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
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+ [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
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+ [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
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+ [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
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+ [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
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+ [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
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+ [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
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+ [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
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+ [RST_BUS_UART5] = RESET(0x90c, BIT(21)),
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+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
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+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
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+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
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+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
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+ [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
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+ [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
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+
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+ [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
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+
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+ [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
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+ [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
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+ [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
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+ [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
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+ [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
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+ [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
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+ [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
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+ [RST_BUS_LRADC] = RESET(0xa9c, BIT(16)),
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+};
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+
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+const struct ccu_desc d1_ccu_desc = {
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+ .gates = d1_gates,
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+ .resets = d1_resets,
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+ .num_gates = ARRAY_SIZE(d1_gates),
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+ .num_resets = ARRAY_SIZE(d1_resets),
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+};
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--- a/drivers/clk/sunxi/clk_sunxi.c
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+++ b/drivers/clk/sunxi/clk_sunxi.c
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@@ -118,6 +118,7 @@ extern const struct ccu_desc a64_ccu_des
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extern const struct ccu_desc a80_ccu_desc;
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extern const struct ccu_desc a80_mmc_clk_desc;
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extern const struct ccu_desc a83t_ccu_desc;
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+extern const struct ccu_desc d1_ccu_desc;
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extern const struct ccu_desc f1c100s_ccu_desc;
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extern const struct ccu_desc h3_ccu_desc;
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extern const struct ccu_desc h6_ccu_desc;
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@@ -183,6 +184,10 @@ static const struct udevice_id sunxi_clk
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{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
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.data = (ulong)&a80_mmc_clk_desc },
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#endif
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+#ifdef CONFIG_CLK_SUN20I_D1
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+ { .compatible = "allwinner,sun20i-d1-ccu",
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+ .data = (ulong)&d1_ccu_desc },
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+#endif
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#ifdef CONFIG_CLK_SUN50I_A64
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{ .compatible = "allwinner,sun50i-a64-ccu",
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.data = (ulong)&a64_ccu_desc },
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--- /dev/null
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+++ b/include/dt-bindings/clock/sun20i-d1-ccu.h
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@@ -0,0 +1,156 @@
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+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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+/*
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+ * Copyright (C) 2020 huangzhenwei@allwinnertech.com
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+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
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+ */
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+
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+#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
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+#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
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+
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+#define CLK_PLL_CPUX 0
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+#define CLK_PLL_DDR0 1
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+#define CLK_PLL_PERIPH0_4X 2
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+#define CLK_PLL_PERIPH0_2X 3
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+#define CLK_PLL_PERIPH0_800M 4
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+#define CLK_PLL_PERIPH0 5
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+#define CLK_PLL_PERIPH0_DIV3 6
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+#define CLK_PLL_VIDEO0_4X 7
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+#define CLK_PLL_VIDEO0_2X 8
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+#define CLK_PLL_VIDEO0 9
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+#define CLK_PLL_VIDEO1_4X 10
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+#define CLK_PLL_VIDEO1_2X 11
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+#define CLK_PLL_VIDEO1 12
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+#define CLK_PLL_VE 13
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+#define CLK_PLL_AUDIO0_4X 14
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+#define CLK_PLL_AUDIO0_2X 15
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+#define CLK_PLL_AUDIO0 16
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+#define CLK_PLL_AUDIO1 17
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+#define CLK_PLL_AUDIO1_DIV2 18
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+#define CLK_PLL_AUDIO1_DIV5 19
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+#define CLK_CPUX 20
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+#define CLK_CPUX_AXI 21
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+#define CLK_CPUX_APB 22
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+#define CLK_PSI_AHB 23
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+#define CLK_APB0 24
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+#define CLK_APB1 25
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+#define CLK_MBUS 26
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+#define CLK_DE 27
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+#define CLK_BUS_DE 28
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+#define CLK_DI 29
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+#define CLK_BUS_DI 30
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+#define CLK_G2D 31
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+#define CLK_BUS_G2D 32
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+#define CLK_CE 33
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+#define CLK_BUS_CE 34
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+#define CLK_VE 35
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+#define CLK_BUS_VE 36
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+#define CLK_BUS_DMA 37
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+#define CLK_BUS_MSGBOX0 38
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+#define CLK_BUS_MSGBOX1 39
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+#define CLK_BUS_MSGBOX2 40
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+#define CLK_BUS_SPINLOCK 41
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+#define CLK_BUS_HSTIMER 42
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+#define CLK_AVS 43
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+#define CLK_BUS_DBG 44
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+#define CLK_BUS_PWM 45
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+#define CLK_BUS_IOMMU 46
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+#define CLK_DRAM 47
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+#define CLK_MBUS_DMA 48
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+#define CLK_MBUS_VE 49
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+#define CLK_MBUS_CE 50
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+#define CLK_MBUS_TVIN 51
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+#define CLK_MBUS_CSI 52
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+#define CLK_MBUS_G2D 53
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+#define CLK_MBUS_RISCV 54
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+#define CLK_BUS_DRAM 55
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+#define CLK_MMC0 56
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+#define CLK_MMC1 57
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+#define CLK_MMC2 58
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+#define CLK_BUS_MMC0 59
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+#define CLK_BUS_MMC1 60
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+#define CLK_BUS_MMC2 61
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+#define CLK_BUS_UART0 62
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+#define CLK_BUS_UART1 63
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+#define CLK_BUS_UART2 64
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+#define CLK_BUS_UART3 65
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+#define CLK_BUS_UART4 66
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+#define CLK_BUS_UART5 67
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+#define CLK_BUS_I2C0 68
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+#define CLK_BUS_I2C1 69
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+#define CLK_BUS_I2C2 70
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+#define CLK_BUS_I2C3 71
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+#define CLK_SPI0 72
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+#define CLK_SPI1 73
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+#define CLK_BUS_SPI0 74
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+#define CLK_BUS_SPI1 75
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+#define CLK_EMAC_25M 76
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+#define CLK_BUS_EMAC 77
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+#define CLK_IR_TX 78
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+#define CLK_BUS_IR_TX 79
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+#define CLK_BUS_GPADC 80
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+#define CLK_BUS_THS 81
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+#define CLK_I2S0 82
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+#define CLK_I2S1 83
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+#define CLK_I2S2 84
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+#define CLK_I2S2_ASRC 85
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+#define CLK_BUS_I2S0 86
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+#define CLK_BUS_I2S1 87
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+#define CLK_BUS_I2S2 88
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+#define CLK_SPDIF_TX 89
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+#define CLK_SPDIF_RX 90
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+#define CLK_BUS_SPDIF 91
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+#define CLK_DMIC 92
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+#define CLK_BUS_DMIC 93
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+#define CLK_AUDIO_DAC 94
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+#define CLK_AUDIO_ADC 95
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+#define CLK_BUS_AUDIO 96
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+#define CLK_USB_OHCI0 97
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+#define CLK_USB_OHCI1 98
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+#define CLK_BUS_OHCI0 99
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+#define CLK_BUS_OHCI1 100
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+#define CLK_BUS_EHCI0 101
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+#define CLK_BUS_EHCI1 102
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+#define CLK_BUS_OTG 103
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+#define CLK_BUS_LRADC 104
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+#define CLK_BUS_DPSS_TOP 105
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+#define CLK_HDMI_24M 106
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+#define CLK_HDMI_CEC_32K 107
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+#define CLK_HDMI_CEC 108
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+#define CLK_BUS_HDMI 109
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+#define CLK_MIPI_DSI 110
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+#define CLK_BUS_MIPI_DSI 111
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+#define CLK_TCON_LCD0 112
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+#define CLK_BUS_TCON_LCD0 113
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+#define CLK_TCON_TV 114
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+#define CLK_BUS_TCON_TV 115
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+#define CLK_TVE 116
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+#define CLK_BUS_TVE_TOP 117
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+#define CLK_BUS_TVE 118
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+#define CLK_TVD 119
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+#define CLK_BUS_TVD_TOP 120
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+#define CLK_BUS_TVD 121
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+#define CLK_LEDC 122
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+#define CLK_BUS_LEDC 123
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+#define CLK_CSI_TOP 124
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+#define CLK_CSI_MCLK 125
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+#define CLK_BUS_CSI 126
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+#define CLK_TPADC 127
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+#define CLK_BUS_TPADC 128
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+#define CLK_BUS_TZMA 129
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+#define CLK_DSP 130
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+#define CLK_BUS_DSP_CFG 131
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+#define CLK_RISCV 132
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+#define CLK_RISCV_AXI 133
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+#define CLK_BUS_RISCV_CFG 134
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+#define CLK_FANOUT_24M 135
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+#define CLK_FANOUT_12M 136
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+#define CLK_FANOUT_16M 137
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+#define CLK_FANOUT_25M 138
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+#define CLK_FANOUT_32K 139
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+#define CLK_FANOUT_27M 140
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+#define CLK_FANOUT_PCLK 141
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+#define CLK_FANOUT0 142
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+#define CLK_FANOUT1 143
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+#define CLK_FANOUT2 144
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+
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+#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
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--- /dev/null
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+++ b/include/dt-bindings/reset/sun20i-d1-ccu.h
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@@ -0,0 +1,77 @@
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+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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+/*
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+ * Copyright (c) 2020 huangzhenwei@allwinnertech.com
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+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
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+ */
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+
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+#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
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+#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
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+
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+#define RST_MBUS 0
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+#define RST_BUS_DE 1
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+#define RST_BUS_DI 2
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+#define RST_BUS_G2D 3
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+#define RST_BUS_CE 4
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+#define RST_BUS_VE 5
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+#define RST_BUS_DMA 6
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+#define RST_BUS_MSGBOX0 7
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+#define RST_BUS_MSGBOX1 8
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+#define RST_BUS_MSGBOX2 9
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+#define RST_BUS_SPINLOCK 10
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+#define RST_BUS_HSTIMER 11
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+#define RST_BUS_DBG 12
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+#define RST_BUS_PWM 13
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+#define RST_BUS_DRAM 14
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+#define RST_BUS_MMC0 15
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+#define RST_BUS_MMC1 16
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+#define RST_BUS_MMC2 17
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+#define RST_BUS_UART0 18
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+#define RST_BUS_UART1 19
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+#define RST_BUS_UART2 20
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+#define RST_BUS_UART3 21
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+#define RST_BUS_UART4 22
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+#define RST_BUS_UART5 23
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+#define RST_BUS_I2C0 24
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+#define RST_BUS_I2C1 25
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+#define RST_BUS_I2C2 26
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+#define RST_BUS_I2C3 27
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+#define RST_BUS_SPI0 28
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+#define RST_BUS_SPI1 29
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+#define RST_BUS_EMAC 30
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+#define RST_BUS_IR_TX 31
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+#define RST_BUS_GPADC 32
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+#define RST_BUS_THS 33
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+#define RST_BUS_I2S0 34
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+#define RST_BUS_I2S1 35
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+#define RST_BUS_I2S2 36
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+#define RST_BUS_SPDIF 37
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+#define RST_BUS_DMIC 38
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+#define RST_BUS_AUDIO 39
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+#define RST_USB_PHY0 40
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+#define RST_USB_PHY1 41
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+#define RST_BUS_OHCI0 42
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+#define RST_BUS_OHCI1 43
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+#define RST_BUS_EHCI0 44
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+#define RST_BUS_EHCI1 45
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+#define RST_BUS_OTG 46
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+#define RST_BUS_LRADC 47
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+#define RST_BUS_DPSS_TOP 48
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+#define RST_BUS_HDMI_SUB 49
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+#define RST_BUS_HDMI_MAIN 50
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+#define RST_BUS_MIPI_DSI 51
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+#define RST_BUS_TCON_LCD0 52
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+#define RST_BUS_TCON_TV 53
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+#define RST_BUS_LVDS0 54
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+#define RST_BUS_TVE 55
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+#define RST_BUS_TVE_TOP 56
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+#define RST_BUS_TVD 57
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+#define RST_BUS_TVD_TOP 58
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+#define RST_BUS_LEDC 59
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+#define RST_BUS_CSI 60
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+#define RST_BUS_TPADC 61
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+#define RST_DSP 62
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+#define RST_BUS_DSP_CFG 63
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+#define RST_BUS_DSP_DBG 64
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+#define RST_BUS_RISCV_CFG 65
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+
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+#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */
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