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https://git.code.sf.net/p/openocd/code
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d8042fbb46
Replace the BSD-3-Clause boilerplate with the SPDX tag. Add the SPDX tag and the copyright to two makefiles that were added by TI with the other files in their respective folder. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I3ad1b2dbdb6054b74dcc26e394c9223ba0427caf Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7158 Tested-by: jenkins
139 lines
5.1 KiB
C
139 lines
5.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/******************************************************************************
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*
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* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
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*
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******************************************************************************/
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#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H
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#define OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Available Peripherals */
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#define __MCU_HAS_FLCTL_A__ /* Module FLCTL_A is available */
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#define __MCU_HAS_SYSCTL_A__ /* Module SYSCTL_A is available */
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/* Device and Peripheral Memory Map */
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#define FLASH_BASE ((uint32_t)0x00000000) /* Flash memory address */
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#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripherals address */
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#define CS_BASE (PERIPH_BASE + 0x00010400) /* Address of CS regs. */
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#define PCM_BASE (PERIPH_BASE + 0x00010000) /* Address of PCM regs. */
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#define RTC_C_BASE (PERIPH_BASE + 0x00004400) /* Address of RTC_C regs */
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#define TLV_BASE ((uint32_t)0x00201000) /* Address of TLV regs. */
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#define WDT_A_BASE (PERIPH_BASE + 0x00004800) /* Address of WDT_A regs */
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#define BITBAND_PERI_BASE ((uint32_t)(0x42000000))
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/*
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* Peripherals with 8-bit or 16-bit register access allow only 8-bit or
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* 16-bit bit band access, so cast to 8 bit always
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*/
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#define BITBAND_PERI(x, b) (*((volatile uint8_t *) (BITBAND_PERI_BASE + \
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(((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4)))
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/* Register map for CLock Signal peripheral (CS) */
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struct cs {
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volatile uint32_t KEY; /* Key Register */
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volatile uint32_t CTL0; /* Control 0 Register */
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volatile uint32_t CTL1; /* Control 1 Register */
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volatile uint32_t CTL2; /* Control 2 Register */
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volatile uint32_t CTL3; /* Control 3 Register */
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};
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/* Register map for Power Control Module peripheral (PCM) */
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struct pcm {
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volatile uint32_t CTL0; /* Control 0 Register */
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volatile uint32_t CTL1; /* Control 1 Register */
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volatile uint32_t IE; /* Interrupt Enable Register */
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volatile uint32_t IFG; /* Interrupt Flag Register */
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volatile uint32_t CLRIFG; /* Clear Interrupt Flag Register */
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};
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/* Register map for Real-Time Clock peripheral (RTC_C) */
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struct rtc_c {
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volatile uint16_t CTL0; /* RTCCTL0 Register */
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volatile uint16_t CTL13; /* RTCCTL13 Register */
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volatile uint16_t OCAL; /* RTCOCAL Register */
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volatile uint16_t TCMP; /* RTCTCMP Register */
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volatile uint16_t PS0CTL; /* RTC Prescale Timer 0 Control Register */
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volatile uint16_t PS1CTL; /* RTC Prescale Timer 1 Control Register */
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volatile uint16_t PS; /* Real-Time Clock Prescale Timer Register */
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volatile uint16_t IV; /* Real-Time Clock Interrupt Vector Register */
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volatile uint16_t TIM0; /* RTCTIM0 Register Hexadecimal Format */
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volatile uint16_t TIM1; /* Real-Time Clock Hour, Day of Week */
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volatile uint16_t DATE; /* RTCDATE - Hexadecimal Format */
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volatile uint16_t YEAR; /* RTCYEAR Register - Hexadecimal Format */
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volatile uint16_t AMINHR; /* RTCMINHR - Hexadecimal Format */
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volatile uint16_t ADOWDAY; /* RTCADOWDAY - Hexadecimal Format */
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volatile uint16_t BIN2BCD; /* Binary-to-BCD Conversion Register */
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volatile uint16_t BCD2BIN; /* BCD-to-Binary Conversion Register */
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};
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/* Register map for Watchdog Timer peripheral (WDT_A) */
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struct wdt_a {
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uint16_t RESERVED0[6];
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volatile uint16_t CTL; /* Watchdog Timer Control Register */
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};
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/* Peripheral Declarations */
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#define CS ((struct cs *) CS_BASE)
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#define PCM ((struct pcm *) PCM_BASE)
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#define RTC_C ((struct rtc_c *) RTC_C_BASE)
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#define WDT_A ((struct wdt_a *) WDT_A_BASE)
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/* Peripheral Register Bit Definitions */
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/* DCORSEL Bit Mask */
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#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000)
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/* Nominal DCO Frequency Range (MHz): 2 to 4 */
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#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000)
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/* Nominal DCO Frequency Range (MHz): 16 to 32 */
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#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000)
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/* CS control key value */
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#define CS_KEY_VAL ((uint32_t)0x0000695A)
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/* AMR Bit Mask */
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#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F)
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/* LPMR Bit Mask */
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#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0)
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/* LPM3.5. Core voltage setting 0. */
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#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0)
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/* LPM4.5 */
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#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0)
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/* CPM Bit Offset */
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#define PCM_CTL0_CPM_OFS (8)
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/* CPM Bit Mask */
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#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00)
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/* PCMKEY Bit Mask */
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#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000)
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/* PMR_BUSY Bit Offset */
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#define PCM_CTL1_PMR_BUSY_OFS (8)
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/* RTCKEY Bit Offset */
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#define RTC_C_CTL0_KEY_OFS (8)
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/* RTCKEY Bit Mask */
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#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00)
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/* RTCHOLD Bit Offset */
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#define RTC_C_CTL13_HOLD_OFS (6)
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/* RTC_C Key Value for RTC_C write access */
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#define RTC_C_KEY ((uint16_t)0xA500)
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/* Watchdog timer hold */
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#define WDT_A_CTL_HOLD ((uint16_t)0x0080)
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/* WDT Key Value for WDT write access */
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#define WDT_A_CTL_PW ((uint16_t)0x5A00)
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/* Address of BSL API table */
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#define BSL_API_TABLE_ADDR ((uint32_t)0x00202000)
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#ifdef __cplusplus
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}
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#endif
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#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H */
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