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https://git.code.sf.net/p/openocd/code
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d8042fbb46
Replace the BSD-3-Clause boilerplate with the SPDX tag. Add the SPDX tag and the copyright to two makefiles that were added by TI with the other files in their respective folder. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I3ad1b2dbdb6054b74dcc26e394c9223ba0427caf Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7158 Tested-by: jenkins
77 lines
2.4 KiB
C
77 lines
2.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/******************************************************************************
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*
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* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
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*
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******************************************************************************/
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#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H
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#define OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define __MCU_HAS_FLCTL__ /* Module FLCTL is available */
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/* Device and peripheral memory map */
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#define FLASH_BASE ((uint32_t)0x00000000) /* Flash memory start address */
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#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM memory start address */
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#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripherals start address */
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#define CS_BASE (PERIPH_BASE + 0x00010400) /* Address of module CS regs. */
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#define DIO_BASE (PERIPH_BASE + 0x00004C00) /* Address of module DIO regs. */
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/* Register map for Clock Signal peripheral (CS) */
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struct cs {
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volatile uint32_t KEY; /* Key Register */
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volatile uint32_t CTL0; /* Control 0 Register */
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volatile uint32_t CTL1; /* Control 1 Register */
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volatile uint32_t CTL2; /* Control 2 Register */
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volatile uint32_t CTL3; /* Control 3 Register */
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};
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/* Register map for DIO port (odd interrupt) */
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struct dio_port_odd_int {
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volatile uint8_t IN; /* Port Input */
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uint8_t RESERVED0;
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volatile uint8_t OUT; /* Port Output */
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};
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/* Register map for DIO port (even interrupt) */
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struct dio_port_even_int {
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uint8_t RESERVED0;
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volatile uint8_t IN; /* Port Input */
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uint8_t RESERVED1;
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volatile uint8_t OUT; /* Port Output */
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};
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/* Peripheral declarations */
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#define CS ((struct cs *) CS_BASE)
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#define P3 ((struct dio_port_odd_int *) (DIO_BASE + 0x0020))
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#define P6 ((struct dio_port_even_int *) (DIO_BASE + 0x0040))
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/* Peripheral bit definitions */
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/* DCORSEL Bit Mask */
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#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000)
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/* Nominal DCO Frequency Range (MHz): 2 to 4 */
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#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000)
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/* Nominal DCO Frequency Range (MHz): 16 to 32 */
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#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000)
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/* CS control key value */
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#define CS_KEY_VAL ((uint32_t)0x0000695A)
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/* Protects Sector 0 from program or erase */
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#define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001)
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/* Protects Sector 1 from program or erase */
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#define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002)
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#ifdef __cplusplus
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}
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#endif
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#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H */
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