mirror of
https://git.code.sf.net/p/openocd/code
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ff550ed0b0
When attempting to write to internal flash the flashing step fails with 'Error: timeout waiting for algorithm, a target reset is recommended'. Updated flashing algorithm for MAX32xxx to fix this. Change-Id: I51350c1320c9699ddcf6cb28d9299538bece4c4f Signed-off-by: Henrik Mau <henrik.mau@analog.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8794 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: zapb <dev@zapb.de>
239 lines
12 KiB
C
239 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2016 by Maxim Integrated *
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* Copyright (C) 2025 Analog Devices, Inc. *
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***************************************************************************/
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#ifndef _FLC_REGS_H_
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#define _FLC_REGS_H_
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/* **** Includes **** */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(__ICCARM__)
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#pragma system_include
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#endif
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/*/ @cond */
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/*/ @endcond */
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/* **** Definitions **** */
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/**
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* @ingroup flc
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* @defgroup flc_registers Registers
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* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
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* @description Flash Memory Control.
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*/
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/**
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* @ingroup flc_registers
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* Structure type to access the FLC Registers.
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*/
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struct mxc_flc_regs {
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__IO uint32_t addr; /**< <tt>\b 0x00:<\tt> FLC ADDR Register */
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__IO uint32_t clkdiv; /**< <tt>\b 0x04:<\tt> FLC CLKDIV Register */
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__IO uint32_t cn; /**< <tt>\b 0x08:<\tt> FLC CN Register */
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__R uint32_t rsv_0xc_0x23[6];
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__IO uint32_t intr; /**< <tt>\b 0x024:<\tt> FLC INTR Register */
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__R uint32_t rsv_0x28_0x2f[2];
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__IO uint32_t data[4]; /**< <tt>\b 0x30:<\tt> FLC DATA Register */
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__O uint32_t acntl; /**< <tt>\b 0x40:<\tt> FLC ACNTL Register */
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};
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/* Register offsets for module FLC */
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/**
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* @ingroup flc_registers
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* @defgroup FLC_Register_Offsets Register Offsets
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* @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address.
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* @{
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*/
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#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0x000 */
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#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0x004 */
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#define MXC_R_FLC_CN ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0x008 */
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#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0x024 */
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#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0x030 */
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#define MXC_R_FLC_ACNTL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0x040 */
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/**@} end of group flc_registers */
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/**
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* @ingroup flc_registers
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* @defgroup ADDR_Register
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* @brief Flash Write Address.
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* @{
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*/
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#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
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#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
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/**@} end of group ADDR_Register */
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/**
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* @ingroup flc_registers
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* @defgroup CLKDIV_Register
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* @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
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* MHz clock for Flash controller.
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* @{
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*/
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#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
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#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
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/**@} end of group CLKDIV_Register */
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/**
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* @ingroup flc_registers
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* @defgroup CN_Register
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* @brief Flash Control Register.
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* @{
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*/
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#define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */
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#define MXC_F_FLC_CN_WR ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */
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#define MXC_V_FLC_CN_WR_COMPLETE ((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value */
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#define MXC_S_FLC_CN_WR_COMPLETE (MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE Setting */
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#define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */
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#define MXC_S_FLC_CN_WR_START (MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */
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#define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */
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#define MXC_F_FLC_CN_ME ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */
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#define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */
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#define MXC_F_FLC_CN_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */
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#define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */
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#define MXC_F_FLC_CN_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */
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#define MXC_V_FLC_CN_WDTH_SIZE128 ((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */
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#define MXC_S_FLC_CN_WDTH_SIZE128 (MXC_V_FLC_CN_WDTH_SIZE128 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */
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#define MXC_V_FLC_CN_WDTH_SIZE32 ((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value */
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#define MXC_S_FLC_CN_WDTH_SIZE32 (MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */
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#define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */
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#define MXC_F_FLC_CN_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */
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#define MXC_V_FLC_CN_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */
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#define MXC_S_FLC_CN_ERASE_CODE_NOP \
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(MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */
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#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */
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#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE \
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(MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting */
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#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */
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#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL \
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(MXC_V_FLC_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting */
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#define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */
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#define MXC_F_FLC_CN_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */
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#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */
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#define MXC_S_FLC_CN_PEND_IDLE (MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE Setting */
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#define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */
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#define MXC_S_FLC_CN_PEND_BUSY (MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */
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#define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */
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#define MXC_F_FLC_CN_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */
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#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */
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#define MXC_S_FLC_CN_LVE_DIS (MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting */
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#define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */
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#define MXC_S_FLC_CN_LVE_EN (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting */
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#define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */
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#define MXC_F_FLC_CN_BRST ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */
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#define MXC_V_FLC_CN_BRST_DISABLE ((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */
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#define MXC_S_FLC_CN_BRST_DISABLE (MXC_V_FLC_CN_BRST_DISABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */
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#define MXC_V_FLC_CN_BRST_ENABLE ((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value */
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#define MXC_S_FLC_CN_BRST_ENABLE (MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */
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#define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */
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#define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */
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#define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */
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#define MXC_S_FLC_CN_UNLOCK_UNLOCKED \
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(MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */
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#define MXC_V_FLC_CN_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CN_UNLOCK_LOCKED Value */
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#define MXC_S_FLC_CN_UNLOCK_LOCKED \
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(MXC_V_FLC_CN_UNLOCK_LOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_LOCKED Setting */
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/**@} end of group CN_Register */
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/**
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* @ingroup flc_registers
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* @defgroup INTR_Register
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* @brief Flash Interrupt Register.
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* @{
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*/
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#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
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#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
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#define MXC_V_FLC_INTR_DONE_INACTIVE ((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */
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#define MXC_S_FLC_INTR_DONE_INACTIVE \
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(MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */
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#define MXC_V_FLC_INTR_DONE_PENDING ((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */
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#define MXC_S_FLC_INTR_DONE_PENDING \
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(MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */
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#define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */
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#define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */
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#define MXC_V_FLC_INTR_AF_NOERROR ((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */
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#define MXC_S_FLC_INTR_AF_NOERROR (MXC_V_FLC_INTR_AF_NOERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */
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#define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */
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#define MXC_S_FLC_INTR_AF_ERROR (MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */
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#define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
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#define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
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#define MXC_V_FLC_INTR_DONEIE_DISABLE ((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */
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#define MXC_S_FLC_INTR_DONEIE_DISABLE \
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(MXC_V_FLC_INTR_DONEIE_DISABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */
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#define MXC_V_FLC_INTR_DONEIE_ENABLE ((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */
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#define MXC_S_FLC_INTR_DONEIE_ENABLE \
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(MXC_V_FLC_INTR_DONEIE_ENABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */
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#define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
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#define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
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/**@} end of group INTR_Register */
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/**
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* @ingroup flc_registers
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* @defgroup DATA_Register
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* @brief Flash Write Data.
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* @{
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*/
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#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
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#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
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/**@} end of group DATA_Register */
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/**
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* @ingroup flc_registers
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* @defgroup ACNTL_Register
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* @brief Access Control Register. Writing the ACNTL register with the following values in
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* the order shown, allows read and write access to the system and user Information
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* block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl =
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* 0x9608b2c1. When unlocked, a write of any word will disable access to system and
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* user information block. Readback of this register is always zero.
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* @{
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*/
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#define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */
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#define MXC_F_FLC_ACNTL_ACNTL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */
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/**@} end of group ACNTL_Register */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _FLC_REGS_H_ */
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