mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-22 10:46:27 +00:00
a126229dff
Replace the GPLv2-or-later boilerplate with the SPDX tag. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I380d552940f1c405309a3346454251c0e80b5a45 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7159 Tested-by: jenkins
164 lines
4.8 KiB
ArmAsm
164 lines
4.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2012 by George Harris *
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* george@luminairecoffee.com *
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m3
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.thumb
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.thumb_func
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/*
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* Params :
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* r0 = start address, status (out)
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* r1 = count
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* r2 = erase command
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* r3 = block size
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*/
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#define SSP_BASE_HIGH 0x4008
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#define SSP_BASE_LOW 0x3000
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#define SSP_CR0_OFFSET 0x00
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#define SSP_CR1_OFFSET 0x04
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#define SSP_DATA_OFFSET 0x08
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#define SSP_CPSR_OFFSET 0x10
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#define SSP_SR_OFFSET 0x0c
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#define SSP_CLOCK_BASE_HIGH 0x4005
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#define SSP_CLOCK_BASE_LOW 0x0000
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#define SSP_BRANCH_CLOCK_BASE_HIGH 0x4005
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#define SSP_BRANCH_CLOCK_BASE_LOW 0x2000
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#define SSP_BASE_CLOCK_OFFSET 0x94
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#define SSP_BRANCH_CLOCK_OFFSET 0x700
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#define IOCONFIG_BASE_HIGH 0x4008
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#define IOCONFIG_BASE_LOW 0x6000
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#define IOCONFIG_SCK_OFFSET 0x18c
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#define IOCONFIG_HOLD_OFFSET 0x190
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#define IOCONFIG_WP_OFFSET 0x194
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#define IOCONFIG_MISO_OFFSET 0x198
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#define IOCONFIG_MOSI_OFFSET 0x19c
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#define IOCONFIG_CS_OFFSET 0x1a0
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#define IO_BASE_HIGH 0x400f
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#define IO_BASE_LOW 0x4000
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#define IO_CS_OFFSET 0xab
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#define IODIR_BASE_HIGH 0x400f
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#define IODIR_BASE_LOW 0x6000
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#define IO_CS_DIR_OFFSET 0x14
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setup: /* Initialize SSP pins and module */
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mov.w r10, #IOCONFIG_BASE_LOW
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movt r10, #IOCONFIG_BASE_HIGH
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mov.w r8, #0xea
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str.w r8, [r10, #IOCONFIG_SCK_OFFSET] /* Configure SCK pin function */
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mov.w r8, #0x40
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str.w r8, [r10, #IOCONFIG_HOLD_OFFSET] /* Configure /HOLD pin function */
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mov.w r8, #0x40
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str.w r8, [r10, #IOCONFIG_WP_OFFSET] /* Configure /WP pin function */
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mov.w r8, #0xed
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str.w r8, [r10, #IOCONFIG_MISO_OFFSET] /* Configure MISO pin function */
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mov.w r8, #0xed
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str.w r8, [r10, #IOCONFIG_MOSI_OFFSET] /* Configure MOSI pin function */
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mov.w r8, #0x44
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str.w r8, [r10, #IOCONFIG_CS_OFFSET] /* Configure CS pin function */
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mov.w r10, #IODIR_BASE_LOW
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movt r10, #IODIR_BASE_HIGH
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mov.w r8, #0x800
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str r8, [r10, #IO_CS_DIR_OFFSET] /* Set CS as output */
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mov.w r10, #IO_BASE_LOW
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movt r10, #IO_BASE_HIGH
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mov.w r8, #0xff
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str.w r8, [r10, #IO_CS_OFFSET] /* Set CS high */
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mov.w r10, #SSP_CLOCK_BASE_LOW
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movt r10, #SSP_CLOCK_BASE_HIGH
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mov.w r8, #0x0000
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movt r8, #0x0100
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str.w r8, [r10, #SSP_BASE_CLOCK_OFFSET] /* Configure SSP0 base clock (use 12 MHz IRC) */
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mov.w r10, #SSP_BRANCH_CLOCK_BASE_LOW
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movt r10, #SSP_BRANCH_CLOCK_BASE_HIGH
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mov.w r8, #0x01
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str.w r8, [r10, #SSP_BRANCH_CLOCK_OFFSET] /* Configure (enable) SSP0 branch clock */
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mov.w r10, #SSP_BASE_LOW
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movt r10, #SSP_BASE_HIGH
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mov.w r8, #0x07
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str.w r8, [r10, #SSP_CR0_OFFSET] /* Set clock postscale */
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mov.w r8, #0x02
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str.w r8, [r10, #SSP_CPSR_OFFSET] /* Set clock prescale */
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str.w r8, [r10, #SSP_CR1_OFFSET] /* Enable SSP in SPI mode */
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write_enable:
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bl cs_down
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mov.w r9, #0x06 /* Send the write enable command */
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bl write_data
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bl cs_up
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bl cs_down
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mov.w r9, #0x05 /* Get status register */
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bl write_data
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mov.w r9, #0x00 /* Dummy data to clock in status */
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bl write_data
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bl cs_up
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tst r9, #0x02 /* If the WE bit isn't set, we have a problem. */
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beq error
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erase:
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bl cs_down
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mov.w r9, r2 /* Send the erase command */
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bl write_data
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write_address:
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lsr r9, r0, #16 /* Send the current 24-bit write address, MSB first */
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bl write_data
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lsr r9, r0, #8
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bl write_data
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mov.w r9, r0
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bl write_data
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bl cs_up
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wait_flash_busy: /* Wait for the flash to finish the previous erase */
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bl cs_down
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mov.w r9, #0x05 /* Get status register */
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bl write_data
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mov.w r9, #0x00 /* Dummy data to clock in status */
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bl write_data
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bl cs_up
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tst r9, #0x01 /* If it isn't done, keep waiting */
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bne wait_flash_busy
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subs r1, r1, #1 /* decrement count */
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cbz r1, exit /* Exit if we have written everything */
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add r0, r3 /* Move the address up by the block size */
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b write_enable /* Start a new block erase */
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write_data: /* Send/receive 1 byte of data over SSP */
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mov.w r10, #SSP_BASE_LOW
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movt r10, #SSP_BASE_HIGH
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str.w r9, [r10, #SSP_DATA_OFFSET] /* Write supplied data to the SSP data reg */
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wait_transmit:
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ldr r9, [r10, #SSP_SR_OFFSET] /* Check SSP status */
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tst r9, #0x0010 /* Check if BSY bit is set */
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bne wait_transmit /* If still transmitting, keep waiting */
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ldr r9, [r10, #SSP_DATA_OFFSET] /* Load received data */
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bx lr /* Exit subroutine */
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cs_up:
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mov.w r8, #0xff
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b cs_write
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cs_down:
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mov.w r8, #0x0000
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cs_write:
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mov.w r10, #IO_BASE_LOW
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movt r10, #IO_BASE_HIGH
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str.w r8, [r10, #IO_CS_OFFSET]
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bx lr
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error:
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movs r0, #0
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exit:
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bkpt #0x00
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.end
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