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Driver for DesignWare SPI controller, found on many SoCs (see compatible list in Linux device tree bindings Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml). This implementation only supports MIPS as it was the only one available for the tests, however, adding support for other architectures should require only few adjustments. Driver relies on flash/nor/spi.h to find Flash chip info. Driver internal functions support 24bit addressing mode, but due to limitations of flash/nor/spi.h, it is not used. The reported writing speed is about 60kb/s. Lint, sanitizer and valgrind reported warnings were not related to the driver. Change-Id: Id3df5626ab88055f034f74f274823051dedefeb1 Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8400 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
314 lines
7.4 KiB
C
314 lines
7.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/**
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* @file
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* Helper functions for DesignWare SPI Core driver.
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* These helpers are loaded into CPU and execute Flash manipulation algorithms
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* at full CPU speed. Due to inability to control nCS pin, this is the only way
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* to communicate with Flash chips connected via DW SPI serial interface.
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*
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* In order to avoid using stack, all functions used in helpers are inlined.
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* Software breakpoints are used to terminate helpers.
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*
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* This file contains functions, common to helpers.
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*/
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#ifndef _DW_SPI_H_
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#define _DW_SPI_H_
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#include <stdint.h>
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#include <sys/param.h>
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#include "../../../../src/helper/types.h"
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/**
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* @brief SI busy status bit.
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*
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* Set when serial transfer is in progress, cleared when master is idle or
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* disabled.
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*/
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#define DW_SPI_STATUS_BUSY 0x01
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/**
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* @brief SI TX FIFO not full status bit.
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*
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* Set when TX FIFO has room for one or more data-word.
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*/
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#define DW_SPI_STATUS_TFNF 0x02
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/**
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* @brief SI TX FIFO empty status bit.
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*/
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#define DW_SPI_STATUS_TFE 0x04
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/**
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* @brief SI RX FIFO not empty status bit.
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*/
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#define DW_SPI_STATUS_RFNE 0x08
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/**
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* @brief Return from helper function.
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*/
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#define RETURN \
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do { \
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asm("sdbbp\n\t"); \
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return; \
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} while (0)
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/**
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* @brief Append byte to TX FIFO.
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*
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* For each transferred byte, DW SPI controller receives a byte into RX FIFO.
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* Slave data are read by pushing dummy bytes to TX FIFO.
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*
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* @param[in] dr: Pointer to DR register.
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* @param[in] byte: Data to push.
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*/
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__attribute__((always_inline)) static inline void
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_send_byte(volatile uint8_t *dr, uint8_t byte)
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{
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*dr = byte;
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}
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/**
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* @brief Get byte from RX FIFO.
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*
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* Reading RX byte removes it from RX FIFO.
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*
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* @param[in] dr: Pointer to DR register.
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* @return RX FIFO byte.
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*/
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__attribute__((always_inline)) static inline uint8_t
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rcv_byte(volatile uint8_t *dr)
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{
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return *dr;
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}
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/**
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* @brief Check transmission is currently in progress.
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*
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* @param[in] sr: Pointer to SR register.
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* @retval 1: Transmission is in progress.
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* @retval 0: Controller is idle or off.
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*/
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__attribute__((always_inline)) static inline int
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tx_in_progress(volatile uint8_t *sr)
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{
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return (*sr ^ DW_SPI_STATUS_TFE) & (DW_SPI_STATUS_BUSY | DW_SPI_STATUS_TFE);
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}
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/**
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* @brief Wait for controller to finish previous transaction.
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*
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* @param[in] sr: Pointer to SR register.
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*/
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__attribute__((always_inline)) static inline void
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wait_tx_finish(volatile uint8_t *sr)
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{
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while (tx_in_progress(sr))
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;
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}
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/**
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* @brief Wait for room in TX FIFO.
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*
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* @param[in] sr: Pointer to SR register.
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*/
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__attribute__((always_inline)) static inline void
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wait_tx_available(volatile uint8_t *sr)
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{
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while (!(*sr & DW_SPI_STATUS_TFNF))
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;
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}
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/**
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* @brief Check for data available in RX FIFO.
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*
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* @param[in] sr: Pointer to SR register.
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* @retval 1: Data available.
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* @retval 0: No data available.
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*/
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__attribute__((always_inline)) static inline int
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rx_available(volatile uint8_t *sr)
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{
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return *sr & DW_SPI_STATUS_RFNE;
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}
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/**
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* @brief Wait for data in RX FIFO.
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*
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* @param[in] sr: Pointer to SR register.
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*/
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__attribute__((always_inline)) static inline void
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wait_rx_available(volatile uint8_t *sr)
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{
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while (!rx_available(sr))
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;
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}
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/**
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* @brief Flush RX FIFO.
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*
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* @param[in] sr: Pointer to SR register.
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* @param[in] dr: Pointer to DR register.
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*/
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__attribute__((always_inline)) static inline void
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flush_rx(volatile uint8_t *sr, volatile uint8_t *dr)
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{
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while (*sr & DW_SPI_STATUS_RFNE)
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*dr;
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}
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/**
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* @brief Append variable number of bytes to TX FIFO.
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*
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* @param[in] sr: Pointer to SR register.
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* @param[in] dr: Pointer to DR register.
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* @param[in] word: Data to append.
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* @param[in] bytes: Number of bytes to append.
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*/
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__attribute__((always_inline)) static inline void
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_send_bytes(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word,
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int bytes)
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{
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for (register int i = bytes - 1; i >= 0; i--) {
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wait_tx_available(sr);
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_send_byte(dr, (word >> (i * 8)) & 0xff);
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}
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}
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/**
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* @brief Append 8 bit value to TX FIFO.
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*
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* @param[in] sr: Pointer to SR register.
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* @param[in] dr: Pointer to DR register.
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* @param[in] word: Data to push.
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*/
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__attribute__((always_inline)) static inline void
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send_u8(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t byte)
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{
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wait_tx_available(sr);
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_send_byte(dr, byte);
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}
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/**
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* @brief Append 24 bit value to TX FIFO.
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*
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* Used to send Flash addresses in 24 bit mode.
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*
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* @param[in] sr: Pointer to SR register.
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* @param[in] dr: Pointer to DR register.
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* @param[in] word: Data to push.
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*/
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__attribute__((always_inline)) static inline void
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send_u24(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word)
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{
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_send_bytes(sr, dr, word, 3);
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}
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/**
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* @brief Append 32 bit value to TX FIFO.
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*
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* @param[in] sr: Pointer to SR register.
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* @param[in] dr: Pointer to DR register.
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* @param[in] word: Data to push.
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*/
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__attribute__((always_inline)) static inline void
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send_u32(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word)
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{
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_send_bytes(sr, dr, word, 4);
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}
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/**
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* @brief Read chip status register.
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*
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* @param[in] sr: Pointer to SR register.
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* @param[in] dr: Pointer to DR register.
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* @param[in] stat_cmd: Read status command.
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* @return Chip status.
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*/
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__attribute__((always_inline)) static inline uint8_t
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read_status(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd)
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{
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wait_tx_finish(sr);
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flush_rx(sr, dr);
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/*
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* Don't bother with wait_tx_available() as TX FIFO is empty
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* and we only send two bytes.
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*/
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_send_byte(dr, stat_cmd);
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_send_byte(dr, 0); // Dummy write to push out read data.
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wait_rx_available(sr);
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rcv_byte(dr); // Dummy read to skip command byte.
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wait_rx_available(sr);
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return rcv_byte(dr);
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}
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/**
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* @brief Enable Flash chip write.
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*
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* @param[in] sr: Pointer to SR register.
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* @param[in] dr: Pointer to DR register.
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* @param[in] we_cmd: Write enable command.
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*/
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__attribute__((always_inline)) static inline void
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write_enable(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t we_cmd)
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{
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wait_tx_finish(sr);
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_send_byte(dr, we_cmd);
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}
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/**
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* @brief Erase Flash sector.
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*
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* @param[in] sr: Pointer to SR register.
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* @param[in] dr: Pointer to DR register.
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* @param[in] erase_cmd: Erase sector cmd.
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* @param[in] address: Sector address.
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* @param[in] four_byte_mode: Device is in 32 bit mode flag.
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*/
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__attribute__((always_inline)) static inline void
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erase_sector(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t erase_cmd,
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uint32_t address, uint8_t four_byte_mode)
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{
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wait_tx_finish(sr);
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_send_byte(dr, erase_cmd);
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if (four_byte_mode)
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send_u32(sr, dr, address);
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else
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send_u24(sr, dr, address);
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}
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/**
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* @brief Wait for write enable flag.
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*
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* @param[in] sr: Pointer to SR register.
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* @param[in] dr: Pointer to DR register.
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* @param[in] stat_cmd: Read status command.
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* @param[in] we_mask: Write enable status mask.
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*/
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__attribute__((always_inline)) static inline void
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wait_write_enable(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd,
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uint8_t we_mask)
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{
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while (!(read_status(sr, dr, stat_cmd) & we_mask))
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;
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}
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/**
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* @brief Wait while flash is busy.
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*
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* @param[in] sr: Pointer to SR register.
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* @param[in] dr: Pointer to DR register.
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* @param[in] stat_cmd: Read status command.
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* @param[in] busy_mask: Flash busy mask.
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*/
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__attribute__((always_inline)) static inline void
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wait_busy(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd,
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uint8_t busy_mask)
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{
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while (read_status(sr, dr, stat_cmd) & busy_mask)
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;
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}
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#endif // _DW_SPI_H_
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