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https://git.code.sf.net/p/openocd/code
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d8042fbb46
Replace the BSD-3-Clause boilerplate with the SPDX tag. Add the SPDX tag and the copyright to two makefiles that were added by TI with the other files in their respective folder. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I3ad1b2dbdb6054b74dcc26e394c9223ba0427caf Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7158 Tested-by: jenkins
199 lines
5.3 KiB
ArmAsm
199 lines
5.3 KiB
ArmAsm
/* SPDX-License-Identifier: BSD-3-Clause */
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/****************************************************************************
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* Copyright (c) 2006 by Michael Fischer. All rights reserved.
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****************************************************************************
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*
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* History:
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*
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* 18.12.06 mifi First Version
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* The hardware initialization is based on the startup file
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* crtat91sam7x256_rom.S from NutOS 4.2.1.
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* Therefore partial copyright by egnite Software GmbH.
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****************************************************************************/
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/*
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* Some defines for the program status registers
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*/
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ARM_MODE_USER = 0x10 /* Normal User Mode */
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ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
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ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
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ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
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ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
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ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
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ARM_MODE_SYS = 0x1F /* System Running in Privileged Operating Mode */
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ARM_MODE_MASK = 0x1F
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I_BIT = 0x80 /* disable IRQ when I bit is set */
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F_BIT = 0x40 /* disable IRQ when I bit is set */
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/*
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* Register Base Address
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*/
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AIC_BASE = 0xFFFFF000
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AIC_EOICR_OFF = 0x130
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AIC_IDCR_OFF = 0x124
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RSTC_MR = 0xFFFFFD08
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RSTC_KEY = 0xA5000000
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RSTC_URSTEN = 0x00000001
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WDT_BASE = 0xFFFFFD40
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WDT_MR_OFF = 0x00000004
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WDT_WDDIS = 0x00008000
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MC_BASE = 0xFFFFFF00
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MC_FMR_OFF = 0x00000060
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MC_FWS_1FWS = 0x00480100
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.section .vectors,"ax"
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.code 32
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/****************************************************************************/
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/* Vector table and reset entry */
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/****************************************************************************/
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_vectors:
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ldr pc, ResetAddr /* Reset */
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ldr pc, UndefAddr /* Undefined instruction */
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ldr pc, SWIAddr /* Software interrupt */
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ldr pc, PAbortAddr /* Prefetch abort */
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ldr pc, DAbortAddr /* Data abort */
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ldr pc, ReservedAddr /* Reserved */
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ldr pc, IRQAddr /* IRQ interrupt */
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ldr pc, FIQAddr /* FIQ interrupt */
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ResetAddr: .word ResetHandler
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UndefAddr: .word UndefHandler
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SWIAddr: .word SWIHandler
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PAbortAddr: .word PAbortHandler
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DAbortAddr: .word DAbortHandler
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ReservedAddr: .word 0
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IRQAddr: .word IRQHandler
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FIQAddr: .word FIQHandler
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.ltorg
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.section .init, "ax"
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.code 32
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.global ResetHandler
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.global ExitFunction
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.extern main
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/****************************************************************************/
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/* Reset handler */
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/****************************************************************************/
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ResetHandler:
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/*
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* The watchdog is enabled after processor reset. Disable it.
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*/
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ldr r1, =WDT_BASE
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ldr r0, =WDT_WDDIS
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str r0, [r1, #WDT_MR_OFF]
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/*
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* Enable user reset: assertion length programmed to 1ms
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*/
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ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
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ldr r1, =RSTC_MR
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str r0, [r1, #0]
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/*
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* Use 2 cycles for flash access.
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*/
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ldr r1, =MC_BASE
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ldr r0, =MC_FWS_1FWS
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str r0, [r1, #MC_FMR_OFF]
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/*
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* Disable all interrupts. Useful for debugging w/o target reset.
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*/
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ldr r1, =AIC_BASE
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mvn r0, #0
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str r0, [r1, #AIC_EOICR_OFF]
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str r0, [r1, #AIC_IDCR_OFF]
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/*
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* Setup a stack for each mode
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*/
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msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
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ldr sp, =__stack_und_end
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msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
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ldr sp, =__stack_abt_end
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msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
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ldr sp, =__stack_fiq_end
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
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ldr sp, =__stack_irq_end
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msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
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ldr sp, =__stack_svc_end
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/*
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* Clear .bss section
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*/
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ldr r1, =__bss_start
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ldr r2, =__bss_end
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ldr r3, =0
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bss_clear_loop:
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cmp r1, r2
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strne r3, [r1], #+4
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bne bss_clear_loop
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/*
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* Jump to main
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*/
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mrs r0, cpsr
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bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
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msr cpsr, r0
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mov r0, #0 /* No arguments */
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mov r1, #0 /* No arguments */
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ldr r2, =main
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mov lr, pc
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bx r2 /* And jump... */
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ExitFunction:
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nop
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nop
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nop
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b ExitFunction
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/****************************************************************************/
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/* Default interrupt handler */
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/****************************************************************************/
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UndefHandler:
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b UndefHandler
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SWIHandler:
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b SWIHandler
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PAbortHandler:
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b PAbortHandler
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DAbortHandler:
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b DAbortHandler
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IRQHandler:
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b IRQHandler
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FIQHandler:
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b FIQHandler
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.weak ExitFunction
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.weak UndefHandler, PAbortHandler, DAbortHandler
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.weak IRQHandler, FIQHandler
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.ltorg
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/*** EOF ***/
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