forked from Openwrt/openwrt
801c88295e
Add the patches with real changes from the binutils 2.40 stable branch. I am not aware that we ran into any of these problems, but I think it is better to take the existing stable patches. They were exported like this: git format-patch binutils-2_40...origin/binutils-2_40-branch I removed the patches changing the version numbers and updating the translations only. I removed the following patches: *Automatic-date-updat* 001-Re-enable-development.-Update-version-to-2.40.0.patch 004-Updated-translations-for-the-gas-and-binutils-sub-di.patch 015-Updated-Swedish-translation-for-the-binutils-sub-dir.patch 027-Updated-Swedish-translation-for-the-binutils-sub-dir.patch Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
116 lines
4.7 KiB
Diff
116 lines
4.7 KiB
Diff
From 27f59ec47a18277b6ea3548f405263ef558f5217 Mon Sep 17 00:00:00 2001
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From: Jan Beulich <jbeulich@suse.com>
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Date: Tue, 31 Jan 2023 09:47:22 +0100
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Subject: [PATCH 26/50] RISC-V: make C-extension JAL available again for
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(32-bit) assembly
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Along with the normal JAL alias, the C-extension one should have been
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moved as well by 839189bc932e ("RISC-V: re-arrange opcode table for
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consistent alias handling"), for the assembler to actually be able to
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use it where/when possible.
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Since neither this nor any other compressed branch insn was being tested
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so far, take the opportunity and introduce a new testcase covering those.
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---
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gas/config/tc-riscv.c | 3 +++
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gas/testsuite/gas/riscv/c-branch-na.d | 20 ++++++++++++++++++++
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gas/testsuite/gas/riscv/c-branch.d | 19 +++++++++++++++++++
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gas/testsuite/gas/riscv/c-branch.s | 11 +++++++++++
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opcodes/riscv-opc.c | 2 +-
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5 files changed, 54 insertions(+), 1 deletion(-)
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create mode 100644 gas/testsuite/gas/riscv/c-branch-na.d
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create mode 100644 gas/testsuite/gas/riscv/c-branch.d
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create mode 100644 gas/testsuite/gas/riscv/c-branch.s
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--- a/gas/config/tc-riscv.c
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+++ b/gas/config/tc-riscv.c
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@@ -2762,6 +2762,8 @@ riscv_ip (char *str, struct riscv_cl_ins
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case 'p':
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goto branch;
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case 'a':
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+ if (oparg == insn->args + 1)
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+ goto jump_check_gpr;
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goto jump;
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case 'S': /* Floating-point RS1 x8-x15. */
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if (!reg_lookup (&asarg, RCLASS_FPR, ®no)
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@@ -3271,6 +3273,7 @@ riscv_ip (char *str, struct riscv_cl_ins
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but the 2nd (with 2 operands) might. */
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if (oparg == insn->args)
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{
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+ jump_check_gpr:
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asargStart = asarg;
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if (reg_lookup (&asarg, RCLASS_GPR, NULL)
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&& (*asarg == ',' || (ISSPACE (*asarg) && asarg[1] == ',')))
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--- /dev/null
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+++ b/gas/testsuite/gas/riscv/c-branch-na.d
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@@ -0,0 +1,20 @@
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+#as: -march=rv32ic
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+#source: c-branch.s
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+#objdump: -drw -Mno-aliases
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+
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+.*:[ ]+file format .*
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+
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+
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+Disassembly of section .text:
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+
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+0+ <target>:
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+[ ]+[0-9a-f]+:[ ]+c001[ ]+c\.beqz[ ]+s0,0 <target>[ ]+0: R_RISCV_RVC_BRANCH .*
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+[ ]+[0-9a-f]+:[ ]+dcfd[ ]+c\.beqz[ ]+s1,0 <target>[ ]+2: R_RISCV_RVC_BRANCH .*
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+[ ]+[0-9a-f]+:[ ]+fc75[ ]+c\.bnez[ ]+s0,0 <target>[ ]+4: R_RISCV_RVC_BRANCH .*
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+[ ]+[0-9a-f]+:[ ]+fced[ ]+c\.bnez[ ]+s1,0 <target>[ ]+6: R_RISCV_RVC_BRANCH .*
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+[ ]+[0-9a-f]+:[ ]+bfe5[ ]+c\.j[ ]+0 <target>[ ]+8: R_RISCV_RVC_JUMP .*
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+[ ]+[0-9a-f]+:[ ]+3fdd[ ]+c\.jal[ ]+0 <target>[ ]+a: R_RISCV_RVC_JUMP .*
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+[ ]+[0-9a-f]+:[ ]+9302[ ]+c\.jalr[ ]+t1
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+[ ]+[0-9a-f]+:[ ]+8382[ ]+c\.jr[ ]+t2
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+[ ]+[0-9a-f]+:[ ]+8082[ ]+c\.jr[ ]+ra
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+#...
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--- /dev/null
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+++ b/gas/testsuite/gas/riscv/c-branch.d
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@@ -0,0 +1,19 @@
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+#as: -march=rv64ic
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+#objdump: -drw
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+
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+.*:[ ]+file format .*
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+
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+
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+Disassembly of section .text:
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+
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+0+ <target>:
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+[ ]+[0-9a-f]+:[ ]+c001[ ]+beqz[ ]+s0,0 <target>[ ]+0: R_RISCV_RVC_BRANCH .*
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+[ ]+[0-9a-f]+:[ ]+dcfd[ ]+beqz[ ]+s1,0 <target>[ ]+2: R_RISCV_RVC_BRANCH .*
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+[ ]+[0-9a-f]+:[ ]+fc75[ ]+bnez[ ]+s0,0 <target>[ ]+4: R_RISCV_RVC_BRANCH .*
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+[ ]+[0-9a-f]+:[ ]+fced[ ]+bnez[ ]+s1,0 <target>[ ]+6: R_RISCV_RVC_BRANCH .*
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+[ ]+[0-9a-f]+:[ ]+bfe5[ ]+j[ ]+0 <target>[ ]+8: R_RISCV_RVC_JUMP .*
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+[ ]+[0-9a-f]+:[ ]+ff7ff0ef[ ]+jal[ ]+0 <target>[ ]+a: R_RISCV_JAL .*
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+[ ]+[0-9a-f]+:[ ]+9302[ ]+jalr[ ]+t1
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+[ ]+[0-9a-f]+:[ ]+8382[ ]+jr[ ]+t2
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+[ ]+[0-9a-f]+:[ ]+8082[ ]+ret
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+#...
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--- /dev/null
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+++ b/gas/testsuite/gas/riscv/c-branch.s
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@@ -0,0 +1,11 @@
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+ .text
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+target:
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+ beq x8, x0, target
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+ beqz x9, target
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+ bne x8, x0, target
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+ bnez x9, target
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+ j target
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+ jal target
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+ jalr x6
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+ jr x7
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+ ret
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--- a/opcodes/riscv-opc.c
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+++ b/opcodes/riscv-opc.c
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@@ -340,9 +340,9 @@ const struct riscv_opcode riscv_opcodes[
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{"jalr", 0, INSN_CLASS_I, "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
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{"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
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{"j", 0, INSN_CLASS_I, "a", MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
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+{"jal", 32, INSN_CLASS_C, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
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{"jal", 0, INSN_CLASS_I, "a", MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
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{"jal", 0, INSN_CLASS_I, "d,a", MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
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-{"jal", 32, INSN_CLASS_C, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
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{"call", 0, INSN_CLASS_I, "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
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{"call", 0, INSN_CLASS_I, "c", (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
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{"tail", 0, INSN_CLASS_I, "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
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