forked from Openwrt/openwrt
a3469a90c4
RISC-V is a new CPU architecture aimed to be fully free and open. This
target will add support for it, based on 5.15.
Supports running on:
- HiFive Unleashed - FU540, first generation
- HiFive Unmatched - FU740, current latest generation, PCIe
SD-card images are generated, where the partitions are required to have
specific type codes. As it is commonplace nowadays, OpenSBI is used as the
first stage, with U-boot following as the proper bootloader.
Specifications:
HiFive Unleashed:
- CPU: SiFive FU540 quad-core RISC-V (U54, RV64IMAFDC or RV64GC)
- Memory: 8Gb
- Ethernet: 1x 10/100/1000
- Console: via microUSB
HiFive Unmatched:
- CPU: SiFive FU740 quad-core RISC-V (U74, RV64IMAFDCB or RV64GCB)
- Memory: 16Gb
- Ethernet: 1x 10/100/1000
- USB: 4x USB 3.2
- PCIe: - 1x PCIe Gen3 x8
- 1x M.2 key M (PCIe x4)
- 1x M.2 Key E (PCIe x1 / USB2.0)
- Console: via microUSB
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
22 lines
362 B
Plaintext
22 lines
362 B
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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#
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# Copyright (C) 2022 OpenWrt.org
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#
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. /lib/functions/uci-defaults.sh
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board_config_update
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case "$(board_name)" in
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sifive,hifive-unleashed-a00)
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ucidef_set_led_netdev "lan" "LAN" "green:d3" "eth0"
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;;
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sifive,hifive-unmatched-a00)
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ucidef_set_led_netdev "lan" "LAN" "green:d2" "eth0"
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;;
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esac
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board_config_flush
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exit 0
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