forked from Openwrt/openwrt
95d3d353f8
Copy patches from patches-6.1 to patches-6.6. No changes. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From: qizhong cheng <qizhong.cheng@mediatek.com>
|
|
Date: Mon, 27 Dec 2021 21:31:10 +0800
|
|
Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
|
|
stabilize
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
|
|
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
|
|
be delayed 100ms (TPVPERL) for the power and clock to become stable.
|
|
|
|
Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
|
|
Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
|
|
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
|
Acked-by: Pali Rohár <pali@kernel.org>
|
|
---
|
|
|
|
--- a/drivers/pci/controller/pcie-mediatek.c
|
|
+++ b/drivers/pci/controller/pcie-mediatek.c
|
|
@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru
|
|
*/
|
|
msleep(100);
|
|
|
|
+ /*
|
|
+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
|
|
+ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
|
|
+ * be delayed 100ms (TPVPERL) for the power and clock to become stable.
|
|
+ */
|
|
+ msleep(100);
|
|
+
|
|
/* De-assert PHY, PE, PIPE, MAC and configuration reset */
|
|
val = readl(port->base + PCIE_RST_CTRL);
|
|
val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
|